1. Pacman: Tolerating Asymmetric Data Races with Unintrusive Hardware
   by Shanxiang Qi, Norimasa Otsuki, Lois Orosa, Abdullah Muzahid, and Josep Torrellas,
   International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides]
2. AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
   by Abdullah Muzahid, Norimasa Otsuki, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2010. [Presentation slides]
3. InstantCheck: Checking the Determinism of Parallel Programs Using On-the-fly Incremental Hashing
   by Adrian Nistor, Darko Marinov, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2010. [Presentation slides]
4. Light64: Lightweight Hardware Support for Data Race Detection during Systematic Testing of Parallel Programs
   by Adrian Nistor, Darko Marinov, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2009. [Presentation slides]
5. SigRace: Signature-Based Data Race Detection
   by Abdullah Muzahid, Dario Suarez, Shanxiang Qi, and Josep Torrellas,
   36th Annual International Symposium on Computer Architecture (ISCA), June 2009. [Presentation slides]
6. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization
   by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
   IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2009.
7. Programming and Debugging Shared Memory Programs with Data Coloring
   by Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, and Josep Torrellas,
   Workshop on Compilers for Parallel Computing (CPC), January 2009.
8. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization
   by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
   13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008. [Presentation slides]
9. PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
   by Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, and Josep Torrellas,
   39th International Symposium on Microarchitecture (MICRO), December 2006.
10. Accurate and Efficient Filtering for the Intel Thread Checker Race Detector
    by Paul Sack, Brian E Bliss, Zhiqiang Ma, Paul Petersen, and Josep Torrellas,
    Workshop on Architectural and System Support for Improving Software Dependability (ASID), October 2006. [Presentation slides]
11. Empowering Software Debugging Through Architectural Support for Program Rollback
    by Radu Teodorescu and Josep Torrellas,
    Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005. [Presentation slides]

12. Deploying Architectural Support for Software Defect Detection in Future Processors
    by Yuanyuan Zhou and Josep Torrellas,
    Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005.

13. Efficient and Flexible Architectural Support for Dynamic Monitoring
    by Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, and Josep Torrellas,
    ACM Transactions on Architecture and Code Optimization (TACO), December 2004.
14. iWatcher: Simple and General Architectural Support for Software Debugging
    by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2004.
15. AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants
    by Pin Zhou, Wei Liu, Fei Long, Shan Lu, Feng Qin, Yuanyuan Zhou, Sam Midkiff and Josep Torrellas,
    37th International Symposium on Microarchitecture (MICRO), December 2004.

16. iWatcher: Efficient Architectural Support for Software Debugging
    by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
    31th Annual International Symposium on Computer Architecture (ISCA), June 2004. [Presentation slides]

17. ReEnact: Using Thread-Level Speculation to Debug Data Races in Multithreaded Codes
    by Milos Prvulovic and Josep Torrellas,
    30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides]