• Papers
    • » Hardware Reliability and Variability
  1. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
    by Radu Teodorescu and Josep Torrellas,
    35th Annual International Symposium on Computer Architecture (ISCA), June 2008.

  2. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
    by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
    IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008.

  3. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
    by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
    40th International Symposium on Microarchitecture (MICRO), December 2007.

  4. ReCycle: Pipeline Adaptation to Tolerate Process Variation
    by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas,
    34th Annual International Symposium on Computer Architecture (ISCA), June 2007.

  5. VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects
    by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas,
    Workshop on Architectural Support for Gigascale Integration (ASGI), June 2007.

  6. Using Register Lifetime Predictions to Protect Register Files Against Soft Errors
    by Pablo Montesinos, Wei Liu, and Josep Torrellas,
    37th International Conference on Dependable Systems and Networks (DSN), June 2007.
    This is an extension of Shield: Cost-Effective Soft-Error Protection for Register Files
    Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006.

  7. Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
    by Brian Greskamp, Smruti Sarangi, and Josep Torrellas,
    International Symposium on Circuits and Systems (ISCAS),
    Special Session: Circuit Design in the Presence of Device Variability, May 2007.

  8. A Model for Timing Errors in Processors with Parameter Variation
    by Smruti Sarangi, Brian Greskamp, and Josep Torrellas,
    8th International Symposium on Quality Electronic Design (ISQED), March 2007.

  9. Patching Processor Design Errors with Programmable Hardware
    by Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2007.

  10. Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
    by Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas,
    39th International Symposium on Microarchitecture (MICRO06), December 2006. Best Paper Award.
    (Presentation slides)

  11. Shield: Cost-Effective Soft-Error Protection for Register Files
    by Pablo Montesinos, Wei Liu, and Josep Torrellas,
    Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC206), October 2006.

  12. Designing Hardware that Supports Cycle-Accurate Deterministic Replay
    by Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas,
    Workshop on Complexity-Effective Design (WCED), June 2006.

  13. CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
    by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
    International Conference on Dependable Systems and Networks (DSN), June 2006.