1. A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency
    by Raghavendra Pothukuchi, Amin Ansari, Bhargava Gopireddy, and Josep Torrellas,
    International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2017. [Presentation slides].
  2. Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks
    by Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa, Ulya Karpuzcu, Radu Teodorescu, Nam Sung Kim, and Josep Torrellas,
    International Symposium on Microarchitecture (MICRO), October 2016. [Presentation slides]
  3. Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures
    by Raghavendra Pothukuchi, Amin Ansari, Petros Voulgaris, and Josep Torrellas,
    International Symposium on Computer Architecture (ISCA), June 2016. [Presentation slides].
    Details on the model and methodology are in A Guide to Design MIMO Controllers for Architectures, Technical Report, April 2016.
  4. ScalCore: Designing a Core for Voltage Scalability
    by Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, and Asit Mishra,
    International Symposium on High Performance Computer Architecture (HPCA), March 2016. [Presentation slides]
  5. Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy
    by Ehsan Totoni, Josep Torrellas, and Laxmikant V. Kale,
    International Conference for High Performance Computing, Networking, Storage and Analysis (SC), November 2014. [Presentation slides]
  6. Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies
    by Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas,
    International Symposium on High Performance Computer Architecture (HPCA), February 2013. [Presentation slides]
  7. Managing Multiple Low-Power Adaptation Techniques: The Positional Approach
    by Michael Huang, Jose Renau and Josep Torrellas,
    Sidebar, Special Issue on Power-Aware Computing, IEEE Computer, December 2003.

  8. Positional Adaptation of Processors: Application to Energy Reduction
    by Michael Huang, Jose Renau, and Josep Torrellas,
    30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides]

  9. Energy-Efficient Hybrid Wakeup Logic
    by Michael Huang, Jose Renau, and Josep Torrellas,
    International Symposium on Low Power Electronics and Design (ISLPED), August 2002. [Presentation slides]

  10. Profile-Based Energy Reduction for High-Performance Processors
    by Michael Huang, Jose Renau, and Josep Torrellas,
    Fourth Workshop on Feedback Directed and Dynamic Optimization (FDDO), December 2001.

  11. The Design of DEETM: A Framework for Dynamic Energy Efficiency and Temperature Management
    by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
    Journal of Instruction-Level Parallelism (JILP), Vol. 3, October 2001.
    A shorter version appeared as
    A Framework for Dynamic Energy Efficiency and Temperature Management
    33rd International Symposium on Microarchitecture (MICRO), December 2000. [Presentation slides]

  12. L1 Data Cache Decomposition for Energy Efficiency
    by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
    International Symposium on Low Power Electronics and Design (ISLPED), August 2001.

  13. A Framework for Dynamic Energy Efficiency and Temperature Management
    by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
    33rd International Symposium on Microarchitecture (MICRO), December 2000. [Presentation slides]
    The power model used is discussed in CSRD Technical Report 1584, October 2000.