2012:

1. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages
   by Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim and Josep Torrellas,
   International Conference on Dependable Systems and Networks (DSN), June 2012. [Presentation slides]
2. Comparing the Power and Performance of Intel's SCC to State-of-the-Art CPUs and GPUs
   by Ehsan Totoni, Babak Behzad, Swapnil Ghike and Josep Torrellas,
   International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2012. [Presentation slides]
3. BulkSMT: Designing SMT Processors for Atomic-Block Execution
   by Xuehai Qian, Benjamin Sahelices and Josep Torrellas,
   International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides]
4. Pacman: Tolerating Asymmetric Data Races with Unintrusive Hardware
   by Shanxiang Qi, Norimasa Otsuki, Lois Orosa, Abdullah Muzahid, and Josep Torrellas,
   International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides]
5. BulkCompactor: Optimized Deterministic Execution via Conflict-Aware Commit of Atomic Blocks
   by Yuelu Duan, Xing Zhou, Wonsun Ahn, and Josep Torrellas,
   International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides]

2011:

1. FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes
   by Rishi Agarwal and Josep Torrellas,
   International Symposium on Computer Architecture (ISCA), June 2011. [Presentation slides]
2. Rebound: Scalable Checkpointing for Coherent Shared Memory
   by Rishi Agarwal, Pranav Garg, and Josep Torrellas,
   International Symposium on Computer Architecture (ISCA), June 2011. [Presentation slides]
3. Thread-Level Speculation
   by Josep Torrellas,
   Encyclopedia of Parallel Computing, Springer Science+Business Media LLC, May 2011.
4. Cache-Only Memory Architecture
   by Josep Torrellas,
   Encyclopedia of Parallel Computing, Springer Science+Business Media LLC, May 2011.

2010:

1. Failure is not an Option: Popular Parallel Programming
   by J.Torrellas, M.Oskin, S.Adve, G.Almasi, L.Ceze, A.Chtchelkanova, C.Das, B.Feiereisen, W.Harrod, M.Hill, J.Hiller, S.Kannan, K.Kant, C.Kozyrakis, J.Larus, R.Murphy, O.Mutlu, S.Narayanasamy, K.Olukotun, Y.Patt, A.Sivasubramaniam, K.Skadron, K.Strauss, S.Swanson, and D.Tullsen,
   Report from the CCC-Sponsored First Workshop on Advancing Computer Architecture Research (ACAR-1),
   released October 2010. [Summary slides]
2. Laying a New Foundation for IT: Computer Architecture for 2025 and Beyond
   by M.Oskin, J.Torrellas, C.Das, J.Davis, S.Dwarkadas, L.Eeckhout, B.Feiereisen, D.Jimenez, M.Hill, M.Kim, J.Larus, M.Martonosi, O.Mutlu, K.Olukotun, A.Putnam, T.Sherwood, J.Smith, D.Wood, and C.Zilles,
   Report from the CCC-Sponsored Second Workshop on Advancing Computer Architecture Research (ACAR-2),
   released December 2010. [Summary slides]
3. ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
   by Xuehai Qian, Wonsun Ahn, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2010. [Presentation slides]
4. AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
   by Abdullah Muzahid, Norimasa Otsuki, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2010. [Presentation slides]
5. InstantCheck: Checking the Determinism of Parallel Programs Using On-the-fly Incremental Hashing
   by Adrian Nistor, Darko Marinov, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2010. [Presentation slides]
6. LeadOut: Composing Low-Overhead Frequency-Enhancing Techniques for Single-Thread Performance in Configurable Multicores
   by Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas,
   16th International Symposium on High-Performance Computer Architecture (HPCA), January 2010. [Presentation slides]

2009:

1. The Bulk Multicore Architecture for Improved Programmability
   by Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, and Milos Prvulovic,
   Communications of the ACM (CACM), December 2009. [Presentation slides]
2. Architectures for Extreme-Scale Computing
   by Josep Torrellas,
   IEEE Computer, November 2009. [Presentation slides]
3. BulkCompiler: High-Performance Sequential Consistency through Cooperative Compiler and Hardware Support
   by Wonsun Ahn, Shanxiang Qi, Jae-Woo Lee, Marios Nicolaides, Xing Fang, Josep Torrellas, David Wong, and Samuel Midkiff,
   International Symposium on Microarchitecture (MICRO), December 2009. [Presentation slides]
4. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration
   by Ulya R. Karpuzcu, Brian Greskamp and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2009. Best Paper Award. [Presentation slides]
5. Light64: Lightweight Hardware Support for Data Race Detection during Systematic Testing of Parallel Programs
   by Adrian Nistor, Darko Marinov, and Josep Torrellas,
   International Symposium on Microarchitecture (MICRO), December 2009. [Presentation slides]
6. Hardware and Software Approaches for Deterministic Multiprocessor Replay of Concurrent Programs
   by Gilles Pokam, Cristiano Pereira, Klaus Danne, Lynda Yang, Samuel King, and Josep Torrellas,
   Intel Technology Journal, Issue on Addressing the Challenges of Tera-Scale Computing, Vol. 13, Issue 4, December 2009.
7. SigRace: Signature-Based Data Race Detection
   by Abdullah Muzahid, Dario Suarez, Shanxiang Qi, and Josep Torrellas,
   36th Annual International Symposium on Computer Architecture (ISCA), June 2009. [Presentation slides]
8. Two Hardware-based Approaches for Deterministic Multiprocessor Replay
   by Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas,
   Research Highlight, Communications of the ACM (CACM), June 2009.
9. Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System
   by Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King, and Josep Torrellas,
   Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), June 2009. [Presentation slides]
10. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization
    by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2009.
11. Capo: A Software-Hardware Interface for Practical Deterministic Multiprocessor Replay
    by Pablo Montesinos, Matthew Hicks, Samuel T. King, and Josep Torrellas,
    14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009. [Presentation slides]
12. BubbleWrap: Popping CMP Cores for Sequential Acceleration
    by Brian Greskamp, R. Ulya Karpuzcu, and Josep Torrellas,
    Wild and Crazy Ideas Session, at 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009. Best Idea Award. [Presentation slides]
13. BlueShift: Designing Processors for Timing Speculation from the Ground Up
    by Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles,
    15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009. [Presentation slides]
14. Programming and Debugging Shared Memory Programs with Data Coloring
    by Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, and Josep Torrellas,
    Workshop on Compilers for Parallel Computing (CPC), January 2009.

2008:

1. Techniques to Mitigate the Effects of Congenital Faults in Processors
   by Smruti R. Sarangi and Josep Torrellas
   160 pages, ISBN: 978-3-639-04637-3, VDM Verlag, 2008.
2. Facelift: Hiding and Slowing Down Aging in Multicores
   by Abhishek Tiwari and Josep Torrellas,
   41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides]
3. EVAL: Utilizing Processors with Variation-Induced Timing Errors
   by Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas,
   41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides]
4. DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently
   by Pablo Montesinos, Luis Ceze, and Josep Torrellas,
   35th Annual International Symposium on Computer Architecture (ISCA), June 2008. [Presentation slides]
5. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
   by Radu Teodorescu and Josep Torrellas,
   35th Annual International Symposium on Computer Architecture (ISCA), June 2008. [Presentation slides]
6. An Updated Evaluation of ReCycle
   by Abhishek Tiwari and Josep Torrellas,
   7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides]
7. Using Register Lifetime Predictions to Protect Register Files Against Soft Errors
   by Pablo Montesinos, Wei Liu, and Josep Torrellas,
   IEEE Transactions on Dependable and Secure Computing (IEEE TDSC), To Appear, 2008.
8. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization
   by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
   13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008. [Presentation slides]
9. Concurrency Control with Data Coloring
   by Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, and Josep Torrellas,
   Workshop on Memory Systems Performance and Correctness (MSPC), March 2008.
10. OpenSPARC: An Open Platform for Hardware Reliability Experimentation
    by Ishwar Parulkar, Alan Wood, James C. Hoe, Babak Falsafi, Sarita Adve, Josep Torrellas, and Subhasish Mitra,
    Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2008. [Presentation slides]
11. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
    by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
    IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008. [Presentation slides]

2007:

1. Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
   by Karin Strauss, Xiaowei Shen, and Josep Torrellas,
   40th International Symposium on Microarchitecture (MICRO), December 2007. [Presentation slides]
2. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
   by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
   40th International Symposium on Microarchitecture (MICRO), December 2007. [Presentation slides]
3. CAP: Criticality Analysis for Power-Efficient Speculative Multithreading
   by James Tuck, Wei Liu, and Josep Torrellas,
   International Conference on Computer Design (ICCD), October 2007. [Presentation slides]
4. Estimating Design Time for System Circuits
   by Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau,
   International Conference on Very Large Scale Integration (VLSI-SoC), October 2007.
5. Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
   by Brian Greskamp and Josep Torrellas,
   International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007. [Presentation slides]
6. BulkSC: Bulk Enforcement of Sequential Consistency
   by Luis Ceze, James M. Tuck, Pablo Montesinos, and Josep Torrellas,
   34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [Presentation slides]
7. ReCycle: Pipeline Adaptation to Tolerate Process Variation
   by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas,
   34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [Presentation slides]
   An updated version with a more realistic pipeline model appears in An Updated Evaluation of ReCycle
   by Abhishek Tiwari and Josep Torrellas,
   7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides]
8. VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects
   by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas,
   Workshop on Architectural Support for Gigascale Integration (ASGI), June 2007.
9. Using Register Lifetime Predictions to Protect Register Files Against Soft Errors
   by Pablo Montesinos, Wei Liu, and Josep Torrellas,
   37th International Conference on Dependable Systems and Networks (DSN), June 2007. [Presentation slides]
   This is an extension of Shield: Cost-Effective Soft-Error Protection for Register Files
   Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006. [Presentation slides]
10. Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
    by Brian Greskamp, Smruti Sarangi, and Josep Torrellas,
    International Symposium on Circuits and Systems (ISCAS),
    Special Session: Circuit Design in the Presence of Device Variability, May 2007. [Presentation slides]
11. A Model for Timing Errors in Processors with Parameter Variation
    by Smruti Sarangi, Brian Greskamp, and Josep Torrellas,
    8th International Symposium on Quality Electronic Design (ISQED), March 2007.
12. Patching Processor Design Errors with Programmable Hardware
    by Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2007.
13. Colorama: Architectural Support for Data-Centric Synchronization
    by Luis Ceze, Pablo Montesinos, Christoph von Praun, and Josep Torrellas,
    13th International Symposium on High-Performance Computer Architecture (HPCA), February 2007. [Presentation slides]

2006:

1. Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
   by Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas,
   39th International Symposium on Microarchitecture (MICRO06), December 2006. Best Paper Award. [Presentation slides]
2. Scalable Cache Miss Handling for High Memory-Level Parallelism
   by James Tuck, Luis Ceze, and Josep Torrellas,
   39th International Symposium on Microarchitecture (MICRO06), December 2006. [Presentation slides]
3. PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
   by Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, and Josep Torrellas,
   39th International Symposium on Microarchitecture (MICRO06), December 2006.
4. Shield: Cost-Effective Soft-Error Protection for Register Files
   by Pablo Montesinos, Wei Liu, and Josep Torrellas,
   Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC206), October 2006. [Presentation slides]
5. Accurate and Efficient Filtering for the Intel Thread Checker Race Detector
   by Paul Sack, Brian E Bliss, Zhiqiang Ma, Paul Petersen, and Josep Torrellas,
   Workshop on Architectural and System Support for Improving Software Dependability (ASID), October 2006. [Presentation slides]
6. Bulk Disambiguation of Speculative Threads in Multiprocessors
   by Luis Ceze, James M. Tuck, Calin Cascaval, and Josep Torrellas,
   33rd Annual International Symposium on Computer Architecture (ISCA), June 2006. [Presentation slides]
7. Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
   by Karin Strauss, Xiaowei Shen, and Josep Torrellas,
   33rd Annual International Symposium on Computer Architecture (ISCA), June 2006. [Presentation slides]
8. Designing Hardware that Supports Cycle-Accurate Deterministic Replay
   by Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas,
   Workshop on Complexity-Effective Design (WCED), June 2006.
9. Rapid Prototyping in Architecture Research Using Hardware Hooks in COTS Systems
   by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
   Workshop on Architectural Research Prototyping (WARP), June 2006.
10. CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
    by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
    International Conference on Dependable Systems and Networks (DSN), June 2006. [Presentation slides]
11. CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses
    by Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas,
    ACM Transactions on Architecture and Code Optimization (TACO), June 2006.

12. SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback
    by Radu Teodorescu, Jun Nakano, and Josep Torrellas,
    IEEE Micro Magazine, IEEE, Inc., vol. 26, September-October, 2006.
13. Are We Ready for High Memory-Level Parallelism?
    by Luis Ceze, James Tuck, and Josep Torrellas,
    Workshop on Memory Performance Issues (WMPI), February 2006. [Presentation slides]
14. Guest Editor's Introduction
    by Josep Torrellas,
    IEEE Micro Magazine, Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
15. POSH: A TLS Compiler that Exploits Program Structure
    by Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas,
    ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006. [Presentation slides]
16. Energy-Efficient Thread-Level Speculation on a CMP
    by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
    IEEE Micro Magazine, Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
17. ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers
    by Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, and Josep Torrellas,
    12th International Symposium on High-Performance Computer Architecture (HPCA), February 2006. [Presentation slides]

2005:

1. uComplexity: Estimating Processor Design Effort
   by Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau,
   Technical Report No. UIUCDCS-R-2005-2644, August 2005.

2. ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
   by Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou,
   38th International Symposium on Microarchitecture (MICRO), November 2005. [Presentation slides]

3. POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure
   by Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas,
   Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. [Presentation slides]

4. A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads
   by Mingliang Wei, Marc Snir, Josep Torrellas, and R. Brett Tremaine
   Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. [Presentation slides]
   Additional details of the Processor can be found in:
   A Brief Description of the NMP ISA and Benchmarks
   by Mingliang Wei, Marc Snir, Josep Torrellas, and R. Brett Tremaine
   Technical Report No. UIUCDCS-R-2005-2633, February 2005.

5. Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multiprocessors
   by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
   ACM Transactions on Architecture and Code Optimization (TACO), September 2005.

6. Thread-Level Speculation on a CMP Can Be Energy Efficient
   by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
   2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides]

7. Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation
   Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas,
   2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides]

8. The Design Complexity of Program Undo Support in a General-Purpose Processor
   by Radu Teodorescu and Josep Torrellas,
   Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA, June 2005. [Presentation slides]

9. Empowering Software Debugging Through Architectural Support for Program Rollback
   by Radu Teodorescu and Josep Torrellas,
   Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005. [Presentation slides]

10. Deploying Architectural Support for Software Defect Detection in Future Processors
    by Yuanyuan Zhou and Josep Torrellas,
    Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005.

11. Prototyping Architectural Support for Program Rollback Using FPGAs
    by Radu Teodorescu and J. Torrellas,
    2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005. [Presentation slides]
    A one-page summary can be found as
    Prototyping Architectural Support for Program Rollback: An Application to Software Debugging
    Workshop on Architecture Research using FPGA Platforms, in conjunction with HPCA-11, February 2005. [Presentation slides]

2004:

1. CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
   by Luis Ceze, Karin Strauss, James Tuck, Jose Renau and Josep Torrellas,
   IEEE Computer Architecture Letters (CAL), IEEE, Inc., December 2004.
2. Efficient and Flexible Architectural Support for Dynamic Monitoring
   by Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, and Josep Torrellas,
   ACM Transactions on Architecture and Code Optimization (TACO), December 2004.
3. iWatcher: Simple and General Architectural Support for Software Debugging
   by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
   IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2004.
4. AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants
   by Pin Zhou, Wei Liu, Fei Long, Shan Lu, Feng Qin, Yuanyuan Zhou, Sam Midkiff and Josep Torrellas,
   37th International Symposium on Microarchitecture (MICRO), December 2004.

5. iWatcher: Efficient Architectural Support for Software Debugging
   by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
   31th Annual International Symposium on Computer Architecture (ISCA), June 2004. [Presentation slides]

2003:

1. Speculative Synchronization
   by Jose Martinez and Josep Torrellas,
   IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2003.

2. High Performance Memory Systems
   by Haldun Hadimioglu, David Kaeli, Jeff Kuskin, Ashwini Nanda and Josep Torrellas, editors
   290 pages, ISBN: 0-387-00310-X, Springer Verlag, New York, 2003.

3. Managing Multiple Low-Power Adaptation Techniques: The Positional Approach
   by Michael Huang, Jose Renau and Josep Torrellas,
   Sidebar, Special Issue on Power-Aware Computing, IEEE Computer, December 2003.

4. Design Trade-offs in High-Throughput Coherence Controllers
   by Anthony Nguyen and Josep Torrellas,
   International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003. [Presentation slides]

5. Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
   by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
   International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003. [Presentation slides]

6. ReEnact: Using Thread-Level Speculation to Debug Data Races in Multithreaded Codes
   by Milos Prvulovic and Josep Torrellas,
   30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides]

7. Positional Adaptation of Processors: Application to Energy Reduction
   by Michael Huang, Jose Renau, and Josep Torrellas,
   30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides]

8. Programming the FlexRAM Parallel Intelligent Memory System
   by Basilio Fraguela, Paul Feautrier, Jose Renau, David Padua, and Josep Torrellas,
   International Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003. [Presentation slides]

9. Correlation Prefetching with a User-Level Memory Thread
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   IEEE Transactions on Parallel and Distributed Computing (TPDS), June 2003.

10. Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    9th International Symposium on High-Performance Computer Architecture (HPCA), February 2003. [Presentation slides]

2002:

1. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
   by José F. Martínez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas,
   35th International Symposium on Microarchitecture (MICRO), November 2002. [Presentation slides]

2. Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications
   by José F. Martínez and Josep Torrellas,
   10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. [Presentation slides]

3. Software Trace Cache for Commercial Applications
   by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero,
   International Journal of Parallel Processing (IJPP), Vol. 30, Number 5, pp. 373-395, October 2002.

4. Energy-Efficient Hybrid Wakeup Logic
   by Michael Huang, Jose Renau, and Josep Torrellas,
   International Symposium on Low Power Electronics and Design (ISLPED), August 2002. [Presentation slides]

5. CFlex: A Programming Language for the FlexRAM Intelligent Memory Architecture
   by Basilio Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas,
   Technical Report UIUCDCS-R-2002-2287, Dept. of Computer Science, UIUC, July 2002.

6. Using a User-Level Memory Thread for Correlation Prefetching
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   29th Annual International Symposium on Computer Architecture (ISCA), May 2002. [Presentation slides]

7. ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
   by Milos Prvulovic, Zheng Zhang, and Josep Torrellas
   29th Annual International Symposium on Computer Architecture (ISCA), May 2002. [Presentation slides]
   In the paper, there is a typo in the Y-Axes of Figs 9 and 10. The corrected plots are here.

8. Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
   by Marcelo Cintra and Josep Torrellas,
   Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002. [Presentation slides]

9. Compiler-Assisted Software and Hardware Support for Reduction Operations
   by F. Dang, M. Garzaran, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger, and J. Torrellas,
   NSF Workshop on Next Generation Systems, April 2002.

2001:

1. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

2. Adaptively Mapping Code in an Intelligent Memory Architecture
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

3. Automatic Code Mapping on an Intelligent Memory Architecture
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001.

4. Prefetching in an Intelligent Memory Architecture Using a Helper Thread
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   Fifth Workshop on Multithreaded Execution, Architecture, and Compilation, December 2001 (Best Paper Award).

5. Profile-Based Energy Reduction for High-Performance Processors
   by Michael Huang, Jose Renau, and Josep Torrellas,
   Fourth Workshop on Feedback Directed and Dynamic Optimization (FDDO), December 2001.

6. The Design of DEETM: A Framework for Dynamic Energy Efficiency and Temperature Management
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   Journal of Instruction-Level Parallelism (JILP), Vol. 3, October 2001.

7. Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors
   by Maria Jesus Garzaran, Milos Prvulovic, Alin Jula, Hao Yu, Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas
   International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001. [Presentation slides]

8. L1 Data Cache Decomposition for Energy Efficiency
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   International Symposium on Low Power Electronics and Design (ISLPED), August 2001.

9. Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
   by Milos Prvulovic, Maria Jesus Garzaran, Lawrence Rauchwerger, and Josep Torrellas,
   28th Annual International Symposium on Computer Architecture (ISCA), June 2001. [Presentation slides]

10. Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors
    by José F. Martínez and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001. [Presentation slides]

11. Software Logging under Speculative Parallelization
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001. [Presentation slides]

12. Exploiting Intelligent Memory for Database Workloads
    by Pedro Trancoso and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001.

13. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
    by Venkata Krishnan and Josep Torrellas,
    International Journal of Parallel Processing (IJPP), Vol. 29, Number 1, pp. 3-33, February 2001.

14. Automatically Mapping Code on an Intelligent Memory Architecture
    by Jaejin Lee, Yan Solihin, and Josep Torrellas,
    Seventh International Symposium on High-Performance Computer Architecture (HPCA), January 2001. [Presentation slides]
    An extended version of it appears in
    IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001.

2000:

1. A Framework for Dynamic Energy Efficiency and Temperature Management
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   33rd International Symposium on Microarchitecture (MICRO), December 2000. [Presentation slides]
   The power model used is discussed in CSRD Technical Report 1584, October 2000.

2. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   2nd Workshop on Intelligent Memory Systems, November 2000.
   It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

3. Adaptively Mapping Code in an Intelligent Memory Architecture
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   2nd Workshop on Intelligent Memory Systems, November 2000.
   It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

4. FlexRAM Architecture Design Parameters
   by Seung-Moon Yoo, Jose Renau, Michael Huang, and Josep Torrellas,
   Center for Supercomputing Research and Development (CSRD) Technical Report 1584, October 2000.

5. Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation
   by Qiang Cao, Josep Torrellas, and H. V. Jagadish
   International Conference on Computer Design (ICCD), September 2000.

6. SmartApps: An Application-Centric Approach to High Performance Computing
   by Lawrence Rauchwerger, Nancy Amato, and Josep Torrellas,
   Thirteen International Workshop on Languages and Compilers for Parallel Computing (LCPC), August 2000.

7. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems
   by Marcelo Cintra, José F. Martínez and Josep Torrellas,
   27th Annual International Symposium on Computer Architecture (ISCA), June 2000. [Presentation slides]

8. Toward a Cost-Effective DSM Organization that Exploits Processor-Memory Integration
   by Josep Torrellas, Liuxi Yang and Anthony-Trung Nguyen,
   Sixth International Symposium on High-Performance Computer Architecture (HPCA), January 2000.

1999:

1. Comprehensive Hardware and Software Support for Operating Systems to Exploit MP Memory Hierarchies
   by Chun Xia and Josep Torrellas,
   IEEE Transactions on Computers, May 1999.

2. A Chip Multiprocessor Architecture with Speculative Multithreading
   by Venkata Krishnan and Josep Torrellas,
   IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999.

3. Excel-NUMA: Toward Programmability, Simplicity, and High Performance
   by Zheng Zhang, Marcelo Cintra, and Josep Torrellas,
   IEEE Transactions on Computers, Special Issue on Cache Memory, February 1999.
   A longer version is CSRD Technical Report 1544, November 1996.

4. FlexRAM: Toward an Advanced Intelligent Memory System
   by Yi Kang, Michael Huang, Seung-Moon Yoo, Zhenzho Ge, Diana Keen, Vinh Lam, Prattap Pattnaik and Josep Torrellas,
   International Conference on Computer Design (ICCD), October 1999. [Presentation slides]

5. Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors
   by Yan Solihin, Vinh Lam, and Josep Torrellas,
   SC 99, November 1999. [Presentation slides]

6. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
   by Venkata Krishnan and Josep Torrellas,
   International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.

7. Cache Optimization for Memory-Resident Decision Support Commercial Workloads
   by Pedro Trancoso and Josep Torrellas
   International Conference on Computer Design (ICCD), October 1999.

8. Detailed Characterization of a Quad Pentium Pro Server Running TPC-D
   by Qiang Cao, Pedro Trancoso, Josep-Lluis Larriba-Pey, Josep Torrellas, Robert Knighten and Youjip Won
   International Conference on Computer Design (ICCD), October 1999.

9. Cache-Only Memory Architectures
   by Fredrik Dahlgren and Josep Torrellas,
   IEEE Computer Magazine, June 1999.

10. Optimization of Instruction Fetch for Decision Support Workloads
    by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Xavi Serrano, Josep Torrellas, and Mateo Valero,
    1999 International Conference on Parallel Processing (ICPP), September 1999.

11. Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors
    by David Koufaty and Josep Torrellas,
    1999 International Conference on Parallel Processing (ICPP), September 1999.

12. Improving the Performance of Bristled CC-NUMA Systems Using Virtual Channels and Adaptivity
    by José F. Martínez, Josep Torrellas, and Jose Duato,
    1999 ACM International Conference on Supercomputing (ICS), June 1999.

13. Software Trace Cache
    by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero,
    1999 ACM International Conference on Supercomputing (ICS), June 1999.

14. Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    Fifth International Symposium on High-Performance Computer Architecture (HPCA), January 1999.

15. Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    First Workshop on Parallel Computing for Irregular Applications, held in conjunction with HPCA-5, January 1999.

16. Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability
    by Josep Torrellas,
    9th SIAM Conference on Parallel Processing for Scientific Computing, March 1999.

17. Hardware for Speculative Parallelization in High-End Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    The Third PetaFlop Workshop (TPF-3), February 1999.

18. Computer Architecture Education at the University of Illinois
    by Josep Torrellas,
    IEEE Computer Architecture Technical Committee Newsletter, February 1999.

1998:

1. Optimizing the Instruction Cache Performance of the Operating System
   by Josep Torrellas, Chun Xia and Russell Daigle,
   IEEE Transactions on Computers, December 1998.
   A shorter version appeared as
   Optimizing Instruction Cache Performance for Operating System Intensive Workloads
   1st International Symposium on High Performance Computer Architecture (HPCA), January 1995.

2. A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors
   by Venkata Krishnan and Josep Torrellas,
   International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1998.

3. Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor
   by Venkata Krishnan and Josep Torrellas,
   International Conference on Supercomputing (ICS), July 1998.

4. Comparing Data Forwarding and Prefetching for Communication-Induced Misses in Shared-Memory MPs
   by David Koufaty and Josep Torrellas,
   International Conference on Supercomputing (ICS), July 1998.

5. An IRAM Architecture for Image Analysis and Pattern Recognition
   by Yi Kang, Josep Torrellas and Tom Huang,
   14th International Conference on Pattern Recognition, 1998.

6. Executing Sequential Binaries on a Multithreaded Architecture with Speculation Support
   by Venkata Krishnan and Josep Torrellas,
   Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98), January 1998.

7. A Clustered Approach to Multithreaded Processors
   by Venkata Krishnan and Josep Torrellas,
   International Parallel Processing Symposium (IPPS), March 1998.

8. Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
   by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
   Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998.

9. Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
   by Sujoy Basu and Josep Torrellas,
   Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998.

1997:

1. The Performance of the Cedar Multistage Switching Network
   by Josep Torrellas and Zheng Zhang,
   IEEE Transactions on Parallel and Distributed Systems (TPDS), April 1997.
   A shorter version appeared as
   The Performance of the Cedar Multistage Switching Network
   Supercomputing'94, November 1994.

2. How Processor-Memory Integration Affects the Design of DSMs
   by Liuxi Yang, Anthony-Trung Nguyen, and Josep Torrellas,
   Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997.

3. Efficient Use of Processing Transistors for Larger On-Chip Storage: Multithreading
   by Venkata Krishnan and Josep Torrellas,
   Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997.

4. The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors
   by Pedro Trancoso, Josep-L. Larriba-Pey, Zheng Zhang, and Josep Torrellas,
   Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997.

5. Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA
   by Zheng Zhang and Josep Torrellas,
   Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997.

6. Speeding up the Memory Hierarchy in Flat COMA Multiprocessors
   by Liuxi Yang and Josep Torrellas,
   Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997.

1996:

1. Data Forwarding in Scalable Shared-Memory Multiprocessors
   by D. A. Koufaty, X. Chen, D. K. Poulsen, and J. Torrellas,
   IEEE Transactions on Parallel and Distributed Systems (TPDS), December 1996.
   A shorter version appeared as
   Data Forwarding in Scalable Shared-Memory Multiprocessors
   1995 International Conference on Supercomputing (ICS), July 1995.

2. The Illinois Aggressive Coma Multiprocessor Project (i-acoma)
   by Josep Torrellas and David Padua,
   6th Symposium on the Frontiers of Massively Parallel Computing, October 1996.

3. An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors
   by Manuel Perez Malumbres(*), Jose Duato(*), and Josep Torrellas,
   (* Universidad Politecnica de Valencia). 1996 Symposium on Parallel and Distributed Processing (SPDP), October 1996.

4. The Augmint Multiprocessor Simulation Toolkit for Intel x86 Architectures,
   by Anthony-Trung Nguyen, Maged Michael, Arun Sharma, and Josep Torrellas,
   1996 International Conference on Computer Design (ICCD), October 1996.

5. The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding
   by Pedro Trancoso and Josep Torrellas,
   1996 International Conference on Parallel Processing (ICPP), August 1996.

6. Computer Architecture Education at the University of Illinois: Current Status and Some Thoughts,
   by Josep Torrellas,
   IEEE Computer Architecture Technical Committee Newsletter, June 1996.

7. Instruction Prefetching of Systems Codes With Layout Optimized for Reduced Cache Misses
   by Chun Xia and Josep Torrellas,
   23rd International Symposium on Computer Architecture (ISCA), June 1996.

8. Optimizing the Primary Cache for Parallel Scientific Applications: The Pool Buffer Approach
   by Liuxi Yang and Josep Torrellas,
   1996 International Conference on Supercomputing (ICS), June 1996.

9. Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors
   by Alain Raynaud, Zheng Zhang, and Josep Torrellas,
   Second International Symposium on High-Performance Computer Architecture (HPCA), January 1996.

10. Improving the Data Cache Performance of Multiprocessor Operating Systems
    by Chun Xia and Josep Torrellas,
    2nd International Symposium on High Performance Computer Architecture (HPCA), January 1996.

1995:

1. Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors,
   by Josep Torrellas, Andrew Tucker and Anoop Gupta,
   Journal of Parallel and Distributed Computing (JPDC), February 1995.

2. Data Forwarding in Scalable Shared-Memory Multiprocessors
   by D. A. Koufaty, X. Chen, D. K. Poulsen, and J. Torrellas,
   1995 International Conference on Supercomputing (ICS), July 1995.

3. Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching,
   by Zheng Zhang and Josep Torrellas,
   22nd International Symposium on Computer Architecture (ISCA), June 1995.

4. Optimizing Instruction Cache Performance for Operating System Intensive Workloads
   by Josep Torrellas, Chun Xia and Russell Daigle,
   1st International Symposium on High Performance Computer Architecture (HPCA), January 1995.

5. Scalable Shared-Memory Architectures: Introduction to MiniTrack,
   by Josep Torrellas,
   28th Hawaii International Conference on System Sciences (HICSS), January 1995.

1994 and Earlier:

1. False Sharing and Spatial Locality in Multiprocessor Caches,
   by Josep Torrellas, Monica S. Lam and John L. Hennessy,
   Transactions on Computers, June 1994.

2. The Performance of the Cedar Multistage Switching Network
   by Josep Torrellas and Zheng Zhang,
   Supercomputing'94, November 1994.

3. An Efficient Algorithm for the Run-time Parallelization of DOACROSS Loops
   by Ding-Kai Chen, Josep Torrellas and Pen-Chung Yew,
   Supercomputing'94, November 1994.

4. Comparing the Performance and Programmibility of the DASH and Cedar Multiprocessors for Scientific Loads
   by Josep Torrellas and David Koufaty, and David Padua,
   1994 International Conference on Parallel Processing (ICPP), August 1994.

5. Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary
   by Josep Torrellas, Andrew Tucker, and Anoop Gupta,
   1993 ACM Sigmetrics Conference, May 1993.

6. Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System
   by Josep Torrellas, Anoop Gupta, and John Hennessy,
   Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 1992.

7. Estimating the Performance Advantages of Relaxing Consistency in a Shared-Memory Multiprocessor
   by Josep Torrellas and John Hennessy,
   1990 International Conference on Parallel Processing (ICPP), August 1990.

8. Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates
   by Josep Torrellas, Monica Lam, and John Hennessy,
   1990 International Conference on Parallel Processing (ICPP), August 1990.

9. Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared-Memory Multiprocessor
   by Josep Torrellas, John Hennessy, and Thierry Weil,
   1990 ACM Sigmetrics Conference, May 1990.