• Papers
    • » Speculative Multithreading
  1. Thread-Level Speculation
    by Josep Torrellas,
    Encyclopedia of Parallel Computing, Springer Science+Business Media LLC, May 2011.

  2. CAP: Criticality Analysis for Power-Efficient Speculative Multithreading
    by James Tuck, Wei Liu, and Josep Torrellas,
    International Conference on Computer Design (ICCD), October 2007. [Presentation slides]

  3. Scalable Cache Miss Handling for High Memory-Level Parallelism
    by James Tuck, Luis Ceze, and Josep Torrellas,
    39th International Symposium on Microarchitecture (MICRO), December 2006. [Presentation slides]

  4. CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses
    by Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas,
    ACM Transactions on Architecture and Code Optimization (TACO), June 2006.

  5. Are We Ready for High Memory-Level Parallelism?
    by Luis Ceze, James Tuck, and Josep Torrellas,
    Workshop on Memory Performance Issues (WMPI), February 2006. [Presentation slides]

  6. POSH: A TLS Compiler that Exploits Program Structure by Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas,
    ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006. [Presentation slides]

  7. Energy-Efficient Thread-Level Speculation on a CMP
    by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.

  8. ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
    by Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou,
    38th International Symposium on Microarchitecture (MICRO), November 2005. [Presentation slides]

  9. POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure
    by Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas,
    Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. [Presentation slides]

  10. Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multiprocessors
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    ACM Transactions on Architecture and Code Optimization (TACO), September 2005.

  11. Thread-Level Speculation on a CMP Can Be Energy Efficient
    by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
    2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides]

  12. Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation
    Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas,
    2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides]

  13. CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
    by Luis Ceze, Karin Strauss, James Tuck, Jose Renau and Josep Torrellas,
    IEEE Computer Architecture Letters (CAL), IEEE, Inc., December 2004.

  14. Speculative Synchronization
    by Jose Martinez and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2003.

  15. Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003. [Presentation slides]

  16. Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    9th International Symposium on High-Performance Computer Architecture (HPCA), February 2003. [Presentation slides]

  17. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
    by José F. Martínez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas,
    35th International Symposium on Microarchitecture (MICRO), November 2002. [Presentation slides]

  18. Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications
    by José F. Martínez and Josep Torrellas,
    10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. [Presentation slides]

  19. Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
    by Marcelo Cintra and Josep Torrellas,
    Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002. [Presentation slides]

  20. Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
    by Milos Prvulovic, Maria Jesus Garzaran, Lawrence Rauchwerger, and Josep Torrellas,
    28th Annual International Symposium on Computer Architecture (ISCA), June 2001. [Presentation slides]

  21. Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors
    by José F. Martínez and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001. [Presentation slides]

  22. Software Logging under Speculative Parallelization
    by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001. [Presentation slides]

  23. The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
    by Venkata Krishnan and Josep Torrellas,
    International Journal of Parallel Processing (IJPP), Vol. 29, Number 1, pp. 3-33, February 2001.
    A shorter version of this paper appeared in International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.

  24. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems
    by Marcelo Cintra, José F. Martínez and Josep Torrellas,
    27th Annual International Symposium on Computer Architecture (ISCA), June 2000.
    [Presentation slides]

  25. Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    Fifth International Symposium on High-Performance Computer Architecture (HPCA), January 1999.

  26. Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    First Workshop on Parallel Computing for Irregular Applications, held in conjunction with HPCA-5, January 1999.

  27. Hardware for Speculative Parallelization in High-End Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    The Third PetaFlop Workshop (TPF-3), February 1999.

  28. Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
    by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
    Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998.

  29. A Chip Multiprocessor Architecture with Speculative Multithreading
    by Venkata Krishnan and Josep Torrellas,
    IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999.

  30. Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor
    by Venkata Krishnan and Josep Torrellas,
    International Conference on Supercomputing (ICS), July 1998.

  31. Executing Sequential Binaries on a Multithreaded Architecture with Speculation Support
    by Venkata Krishnan and Josep Torrellas,
    Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98), January 1998.

  32. A Clustered Approach to Multithreaded Processors
    by Venkata Krishnan and Josep Torrellas,
    International Parallel Processing Symposium (IPPS), March 1998.

  33. Efficient Use of Processing Transistors for Larger On-Chip Storage: Multithreading
    by Venkata Krishnan and Josep Torrellas,
    Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997.