Professor Josep Torrellas
Saburo Muroga Professor of Computer Science
University of Illinois at Urbana-Champaign
(torrella@illinois.edu) Google Scholar, CV June 2021













Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He is the Director of the Center for Programmable Extreme-Scale Computing, a Co-Leader of the Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC).

Torrellas has made many contributions to shared-memory multiprocessor architectures and thread-level speculation (TLS) over more than thirty years. He was the first to apply TLS ideas to parallel architectures and programs: He used speculative multithreading to eliminate stalling due to synchronization (Speculative Synchronization), identify and debug data races (ReEnact), monitor memory accesses (I-Watcher), provide fault tolerance (ReVive), and inexpensively enforce sequential consistency (BulkSC). Some of these ideas impacted IBM's Blue Gene and other commercial machines. Torrellas was part of the design team of IBM’s PERCS Multiprocessor, an architecture for productivity. The team incorporated some of his TLS mechanisms, as well as processing-in-memory features inspired by his FlexRAM Intelligent Memory project.

Using mechanisms inspired by TLS, Torrellas developed the Bulk Architecture, an out-of-the-box scalable shared-memory multiprocessor for programmability that was influential within Intel as part of the Illinois-Intel Parallelism Center. Torrellas also applied TLS ideas to develop Record and deterministic Replay (RnR) architectures and, together with Intel, he built QuickRec, the first RnR hardware prototype, which used FPGAs to extend Intel’s cores and caches for RnR.

Torrellas has made many other contributions to multiprocessor architectures, NUMA organizations, cache coherence protocols, hardware synchronization, and prefetching schemes. In recognition, the government made his I-ACOMA multiprocessor one of the Ten Design-Point Studies funded nationwide to attain Petaflop machines. He was involved in the Stanford DASH and Illinois Cedar experimental multiprocessors. His early work on false sharing and cache behavior of OS and commercial workloads influenced compiler writers and architects of early parallel machines, such as the Silicon Graphics Origin2000. Torrellas was also co-leader of the Intel Runnemede Extreme-Scale manycore, a multiprocessor designed for energy efficiency that impacted Intel’s high-end architectures.

Torrellas received the 2021 IEEE Computer Society Harry H. Goode Memorial Award ”for contributions to energy efficient and programmable shared-memory multiprocessor architectures”, the 2017 UIUC Campus Award for Excellence in Graduate Student Mentoring, and the 2015 IEEE Computer Society Technical Achievement Award ”for pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation”. He has received a Google Faculty Research Award, IBM Partnership Awards, Intel Research Council Awards, and an NSF Young Investigator Award. He is a Fellow of IEEE (2004), ACM (2010), and AAAS (2016). He has received many Best Paper Awards and a High-Impact Paper Award.

Torrellas has mentored generations of computer architects. Of his 43 Ph.D. graduates, over a dozen are faculty at top US academic institutions, including Martínez (Cornell), Solihin (UCF), Huang (Rochester), Prvulovic (Gatech), Renau (UCSC), Tuck (NCSU), Ceze (Washington), Teodorescu (OSU), Ahn (Pittsburgh), Muzahid (Texas A&M), Karpuzcu (Minnesota), Qian (USC), Honarmand (Stony Brook), Yan (MIT), and Skarlatos (CMU).

Torrellas is currently the Chair of the IEEE CS Technical Committee on Computer Architecture (TCCA). He has served in the Board of Directors of the Computing Research Association (CRA) (2016-19), and has been a Council Member of CRA’s Computing Community Consortium (CCC) (2011-14). He serves in the International Roadmap for Devices and Systems (IRDS), and is a Member of the U.S. National Academies Board on Army Research and Development. He has co-organized many funding and visioning workshops. His workshops on Advancing Computer Architecture Research helped usher NSF’s XPS Program.

Prior to being at UIUC, Torrellas received a Ph.D. from Stanford University.



Torrellas leads The i-acoma Architecture Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. Two examples of projects we have done in the past:

Examples of Architectures We Designed in the Past:

Recent News (whole list at the News Tab):

Some Recent Publications:

Software Released:

  • VARIUS and VARIUS-NTV: A model of within-die process variation and resulting timing errors in manycores for microarchitects.
  • SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.

Emphasis Research Areas:

The main emphasis research areas in the group are:

Currently Teaching:

CS533: Parallel Computer Architectures.

Contact Information

Josep Torrellas
4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrella@illinois.edu

Administrative Assistant

Madeleine Garvey,
Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 300-6342.
E-mail: mgarvey@illinois.edu

Our research is funded by NSF, DARPA, and DOE.