The i-acoma group at UIUC

Josep Torrellas (torrellas at cs.uiuc.edu)

Torrellas leads the i-acoma architecture group
The main emphasis is on designing The Bulk Multicore Architecture (Communications of the ACM, December 2009).
See presentation slides on the Bulk Multicore Architecture
Read the EE Times article that discusses the Bulk Multicore
Read the Dr. Dobb's Journal discussion of the Bulk Multicore

Recent News:

• Decemeber 2009: Our paper The BubbleWrap Many-Core: Burning Cores for Sequential Acceleration receives the Best Paper Award at the International Conference on Microarchitecture (MICRO), New York, December 2009.
• February 22-23, 2010: Josep Torrellas co-organizes a Workshop on Advancing Parallel Computer Architecture Research, sponsored by the Computing Research Association (CRA) Computing Community Consortium (CCC) in San Diego, CA.
• January 11, 2010: Josep Torrellas organizes a panel at HPCA 2010 in Bangalore on Extreme Scale Computing: Challenges and Opportunities.
• January 9-10, 2010: Josep Torrellas co-organizes an NSF-sponsored workshop to discuss collaboration in research and education between researchers in India and the U.S. in the area of parallel and high-performance computing.
• January 2010: Our group publishes a paper in HPCA
• December 2009: Our group publishes an article in the December 2009 issue of the Communications of the ACM on The Bulk Multicore Architecture for Improved Programmability
• November 2009: Josep Torrellas publishes an article in the November 2009 issue of IEEE Computer on Architectures for Extreme-Scale Computing.
• August 2009: Our group has three papers accepted at the International Conference on Microarchitecture (MICRO), New York, December 2009.

Some Recent Publications:

• LeadOut: Composing Low-Overhead Frequency-Enhancing Techniques for Single-Thread Performance in Configurable Multicores, HPCA, January 2010.
• The Bulk Multicore Architecture for Improved Programmability, CACM, December 2009. Presentation slides.
• Architectures for Extreme-Scale Computing, IEEE Computer, November 2009.
• BulkCompiler: High-Performance Sequential Consistency through Cooperative Compiler and Hardware Support, MICRO, December 2009.
• The BubbleWrap Many-Core: Burning Cores for Sequential Acceleration, MICRO, December 2009. Best Paper Award.
  (Presentation slides)
• Light64: Lightweight Hardware Support for Race Detection during Systematic Testing of Parallel Programs, MICRO, December 2009.

Software Released:

• VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
• SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.

Research Interests:

Professor Torrellas leads The i-acoma Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The goal is to design high-performance multiprocessor computers that are very easy to program, inexpensive, and built out of commodity components.

The main emphasis is on several areas:

• Multiprocessor organization and system design
• Speculative multithreading
• Hardware reliability and variability
• Support for software reliability
• Low-power design
• Old Projects
• The FlexRAM Intelligent Memory System
• The Morphable Multithreaded Memory Tiles (M3T) architecture

Professor Torrellas is also involved in the related project The Polaris parallelizing compiler.

Currently Teaching:

CS533: Parallel Computer Architectures.

Contact Information

Josep Torrellas
4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrellas@cs.uiuc.edu.

Administrative Assistant

Karen Hipskind,
Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-6621, fax 217-265-6582.
E-mail: hipskind@uiuc.edu.