Josep Torrellas (torrellas at cs.uiuc.edu)
Professor and Willett Faculty Scholar
Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign (UIUC)
Willett Faculty Scholar, 2002-present
IEEE Fellow, 2004
National Science Foundation Young Investigator Award, 1994
Ph.D. in Electrical Engineering, Stanford University, 1992
Chair, IEEE Technical Committee on Computer Architecture
Graduated 25 Ph.D. students, now leaders in academia and industry
Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign (UIUC)
Willett Faculty Scholar, 2002-present
IEEE Fellow, 2004
National Science Foundation Young Investigator Award, 1994
Ph.D. in Electrical Engineering, Stanford University, 1992
Chair, IEEE Technical Committee on Computer Architecture
Graduated 25 Ph.D. students, now leaders in academia and industry
- « Publications »
- « Curriculum Vitae »
- « Students Graduated»
Torrellas leads the i-acoma architecture group.
The main emphasis is on designing The Bulk Multicore Architecture.
See our White
Paper on the Bulk Multicore Architecture (To appear in the
Communications of the ACM in 2009).
See presentation
slides on the Bulk Multicore Architecture
See the
EE Times article that discusses the Bulk Multicore.
I am graduating 2 excellent Ph.D. students, who are now looking for a job starting Fall 2009: Brian Greskamp , and Pablo Montesinos . Please check their resumes.
Some Recent Publications:
- The Bulk Multicore for Improved Programmability, CACM, December 2009. Presentation slides.
- SigRace: Signature-Based Data Race Detection, ISCA, June 2009.
- Two Hardware-based Approaches for Deterministic Multiprocessor Replay, Research Highlight, CACM, June 2009.
- Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System, WIOSCA, June 2009.
- SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimizationm by IEEE Micro Top Picks, January-February 2009.
- Capo: A Software-Hardware Interface for Practical Deterministic Multiprocessor Replay, ASPLOS, March 2009.
- BubbleWrap: Popping CMP Cores for Sequential Acceleration, Wild and Crazy Ideas, ASPLOS, March 2009.
Software Released:
- VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
- SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.
Research Interests:
Professor Torrellas leads The i-acoma Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The goal is to design high-performance multiprocessor computers that are very easy to program, inexpensive, and built out of commodity components.The main emphasis is on several areas:
- Multiprocessor organization and system design
- Speculative multithreading
- Hardware reliability and variability
- Support for software reliability
- Low-power design
- Old Projects
Professor Torrellas is also involved in the related project The Polaris parallelizing compiler.
Currently Teaching:
CS533: Parallel Computer Architectures.Contact Information
Josep Torrellas4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrellas@cs.uiuc.edu.
Administrative Assistant
Sheila Clark,Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-6621, fax 217-265-6582.
E-mail: sdclark@cs.uiuc.edu.