Josep Torrellas (torrella at illinois.edu)
We are graduating 2 excellent Ph.D. students, who are now looking
for an academic or research job starting Fall 2012:
Ulya Karpuzcu,
and
Abdullah Muzahid .
Please check their resumes.
NEW: Torrellas is the Program Chair of ISCA-2012
(Call for Papers).
Josep Torrellas is a Professor at the Departments of Computer Science and
(by courtesy) Electrical and Computer Engineering at the University of
Illinois at Urbana-Champaign. He is the Director of the Center for
Programmable Extreme Scale Computing, and the Director of the Illinois-Intel Parallelism
Center (I2PC). He is a Fellow of IEEE (2004) and ACM (2010). He was a
Willett Faculty Scholar at UIUC (2002-2009) and the Chair of the
IEEE Technical Committee on Computer Architecture (2005-2010).
As of 2010, he has graduated 27 Ph.D. students, who are now leaders in academia and
industry.
- « Publications »
- « Curr. Vitae »
- « Students Graduated»
Torrellas leads The i-acoma Architecture Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The two main projects are:
- A novel multicore architecture for programmability:
The Bulk Multicore Architecture (Communications of the ACM,
December 2009).
[Presentation slides].
EE Times article that discusses the Bulk Multicore.
Dr. Dobb's Journal discussion of the Bulk Multicore.
This project is funded under the Illinois-Intel Parallelism Center (I2PC). - An extreme-scale multiprocessor architecture designed from the
ground up for energy and power efficiency:
Thrifty: An Extreme-Scale Multiprocessor Architecture
(IEEE Computer, November 2009).
[Presentation slides].
This work is part of an Intel-lead DARPA project that aims to design an Extreme-Scale computer.
Intel blog on the DARPA project.
This project is funded by DARPA under UHPC and DOE.
Recent News:
- November 2011: Our research group has three papers accepted at the International Symposium on High Performance Computer Architecture (HPCA), New Orleans, LA, February 2012.
- July 2011: Josep Torrellas is the Program Chair of ISCA-2012 (Call for Papers).
- June 2011: Josep Torrellas will moderate a panel on "Broadening Computer Architecture Research: Embracing New Areas to Keep the Field Vibrant" at the International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011 .
- April 2011: Abdullah Muzahid, one of the graduate students in our group, has been awarded an Intel PhD Fellowship and a Mavis Future Faculty Fellows (MF3) award (an award to facilitate the training of the next generation of great engineering professors).
- February 2011: Our research group has two papers accepted at the International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011 .
- December 2010: Josep Torrellas is named ACM Fellow.
- October 2010: We released Failure is not an Option: Popular Parallel Programming, the report from the First Workshop on Advancing Computer Architecture Research (ACAR-1), which was sponsored by the Computing Community Consortium (CCC). [Summary slides]. More information can be obtained from http://iacoma.cs.uiuc.edu/acar1.
Some Recent Publications:
- VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages, DSN, June 2012. [Presentation slides]
- Comparing the Power and Performance of Intel's SCC to State-of-the-Art CPUs and GPUs, ISPASS, April 2012. [Presentation slides]
- BulkSMT: Designing SMT Processors for Atomic-Block Execution, HPCA, February 2012. [Presentation slides]
- Pacman: Tolerating Asymmetric Data Races with Unintrusive Hardware, HPCA, February 2012. [Presentation slides]
- BulkCompactor: Optimized Deterministic Execution via Conflict-Aware Commit of Atomic Blocks, HPCA, February 2012. [Presentation slides]
- FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes, ISCA, June 2011. [Presentation slides]
- Rebound: Scalable Checkpointing for Coherent Shared Memory, ISCA, June 2011. [Presentation slides]
Software Released:
- VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
- SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.
Emphasis Research Areas:
The main emphasis research areas in the group are:
- Multiprocessor organization and system design
- Speculative multithreading
- Hardware reliability and variability
- Support for software reliability
- Low-power design
- Old Projects
Currently Teaching:
CS533: Parallel Computer Architectures.Contact Information
Josep Torrellas4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 244-4148, fax 217-265-6582.
E-mail: torrella@illinois.edu
Administrative Assistant
Sherry Unkraut,Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 244-6621, fax 217-265-6582.
E-mail: sunkraut@illinois.edu