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  1. FlexRAM: Toward an Advanced Intelligent Memory System. A Retrospective Paper
    by Josep Torrellas,
    International Conference on Computer Design (ICCD), September 2012. [Presentation slides]
  2. Programming the FlexRAM Parallel Intelligent Memory System
    by Basilio Fraguela, Paul Feautrier, Jose Renau, David Padua, and Josep Torrellas,
    International Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003. [Presentation slides]

  3. Correlation Prefetching with a User-Level Memory Thread
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    IEEE Transactions on Parallel and Distributed Computing (TPDS), June 2003.

  4. CFlex: A Programming Language for the FlexRAM Intelligent Memory Architecture
    by Basilio Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas,
    Technical Report UIUCDCS-R-2002-2287, Dept. of Computer Science, UIUC, July 2002.

  5. Using a User-Level Memory Thread for Correlation Prefetching
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    29th Annual International Symposium on Computer Architecture (ISCA), May 2002. [Presentation slides]
    A preliminary version appeared at
    Prefetching in an Intelligent Memory Architecture Using a Helper Thread,
    The Fifth Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC), December 2001 (Best Paper Award).

  6. Automatically Mapping Code on an Intelligent Memory Architecture
    by Jaejin Lee, Yan Solihin, and Josep Torrellas,
    Seventh International Symposium on High-Performance Computer Architecture (HPCA), January 2001. [Presentation slides]
    An extended version of it appears in
    Automatic Code Mapping on an Intelligent Memory Architecture
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001.

  7. Exploiting Intelligent Memory for Database Workloads
    by Pedro Trancoso and Josep Torrellas,
    Workshop on Memory Performance Issues, June 2001.

  8. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
    by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
    2nd Workshop on Intelligent Memory Systems, November 2000.
    It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

  9. Adaptively Mapping Code in an Intelligent Memory Architecture
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    2nd Workshop on Intelligent Memory Systems, November 2000.
    It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

  10. FlexRAM Architecture Design Parameters
    by Seung-Moon Yoo, Jose Renau, Michael Huang, and Josep Torrellas,
    Center for Supercomputing Research and Development (CSRD) Technical Report 1584, October 2000.

  11. Toward a Cost-Effective DSM Organization that Exploits Processor-Memory Integration
    by Josep Torrellas, Liuxi Yang and Anthony-Trung Nguyen,
    Sixth International Symposium on High-Performance Computer Architecture (HPCA), January 2000.

  12. FlexRAM: Toward an Advanced Intelligent Memory System
    by Yi Kang, Michael Huang, Seung-Moon Yoo, Zhenzho Ge, Diana Keen, Vinh Lam, Prattap Pattnaik and Josep Torrellas,
    International Conference on Computer Design (ICCD), October 1999. [Presentation slides]

  13. An IRAM Architecture for Image Analysis and Pattern Recognition
    by Yi Kang, Josep Torrellas and Tom Huang,
    14th International Conference on Pattern Recognition, 1998.

  14. How Processor-Memory Integration Affects the Design of DSMs
    by Liuxi Yang, Anthony-Trung Nguyen, and Josep Torrellas,
    Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997.