Biography of Josep Torrellas

Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He is the Director of the Center for Programmable Extreme Scale Computing, and past Director of the Illinois-Intel Parallelism Center (I2PC). He was also the Coordinator of the UIUC OpenSPARC Center of Excellence. He is a Fellow of IEEE (2004) and ACM (2010). He received the IEEE Computer Society 2015 Technical Achievement Award, for "Pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation". He is a member of the Computing Research Association (CRA) Board of Directors.


Prof. Torrellas' research interests are shared-memory parallel computer architecture, low-power architectures, hardware reliability, and software dependability. In the area of shared-memory architecture, he has contributed with designs for Thread-Level Speculation; Speculative Synchronization; cache hierarchy organizations for software debugging, monitoring, and high-performance sequential consistency; embedded-ring snoopy cache-coherence protocols; incremental, in-memory checkpointing; and early models of data sharing. In hardware reliability, he has contributed with models of process variation and wearout (VARIUS and Facelift); a framework to trade-off wearout for power and performance (Bubble-Wrap); novel techniques to tackle process variation; and a scheme to recover from design bugs. In the area of software dependability, he has proposed new techniques for deterministic replay of parallel programs, data-race and atomicity violation detection, and address disambiguation. His group has also developed two popular multiprocessor architecture simulation packages, namely Augmint and SESC. He has published over 200 publications, many in the most competitive venues, and received 13 Best Paper awards.


His current research projects are The Bulk Multicore Architecture for parallel programming productivity, and The Thrifty-Runnemede Extreme Scale Architecture. The Bulk architecture uses a novel execution model based on continuous execution of atomic blocks that enables a friendly environment for program development and debugging. The Thrifty-Runnemede architecture is designed from the ground up for energy and power efficiency.


Prof. Torrellas has been involved in many influential projects in multiprocessor computer architecture. He lead the Illinois Aggressive Cache Only Memory Architecture (I-ACOMA) design, which was one of the Ten Point-Design Studies funded by the federal government in the nineties to accelerate the arrival of a petascale machine. He lead the DARPA-funded M3T Polymorphic Computer Architecture, and co-directed the NSF-funded FlexRAM Intelligent Memory project. He was one of the PIs in the DARPA-funded IBM PERCS multiprocessor project, which lead to the design of the IBM Blue Waters supercomputer at NCSA. He has been a co-PI of the DARPA-funded Intel Runnemede multiprocessor, developed under the Ubiquitous High Performance Computing program. Before that, Torrellas contributed to the Stanford DASH and Illinois Cedar experimental multiprocessors.


As of 2016, Prof. Torrellas has graduated 36 Ph.D. students, of whom 13 are now Assistant or Associate Professors at leading US universities, including Cornell University, University of Washington, Georgia Tech, NCSU, UCSC, University of Rochester, Ohio State University, University of Minnesota, University of Texas San Antonio, Stony Brook University, University of Pittsburgh, and University of Southern California. Of them, 8 have NSF CAREER Awards.


Prof. Torrellas has served the architecture community extensively. He is now a member of the Computing Research Association (CRA) Board of Directors. From 2005 to 2010, he served as Chair of IEEE Technical Committee on Computer Architecture, where he contributed in a myriad of professional advancement activities. He served as Vice-Chair in the prior four years and continues to serve in the Advisory Board. He was a Council Member of CRA's Computing Community Consortium (CCC) from 2011 to 2014. Prof. Torrellas has served in many initiatives from DARPA, NSF, DOE, NSA, NASA and CRA. For example, he co-organized two workshops on Advancing Computer Architecture Research (here and here), and co-edited a white paper on 21st Century Computer Architecture. Torrellas has served in the organization of numerous professional conferences and workshops. Recent major service includes Program Chair of PACT 2014, ISCA 2012, HPCA 2005, IEEE-Micro Top Picks 2005, and SC 2007; Program Vice-Chair of Architecture in ICPP 2001, IPDPS 2003 and SC 2003; General Chair of HPCA 2000, PPoPP 2006 and PACT 2005; and Vice-General Chair of COOL Chips in 2009-2012. For many years, he has co-organized two influential yearly workshops on Scalable Shared-Memory Multiprocessors and Computer Architecture Evaluation Using Commercial Workloads. He regularly serves in Program Committees of conferences.


Prof. Torrellas was a Willett Faculty Scholar at UIUC from 2002 to 2009. He has received two Xerox Awards for Outstanding Faculty Research, an NSF Young Investigator Award, a Gear Outstanding Junior Faculty Award, an IBM Partnership Award, and an NSF Research Initiation Award. He received the High-Impact Paper Award in October 2012 for "One of the 5 most cited papers in the first 30 years of ICCD".


Torrellas received a Ph.D. from Stanford University and spent a sabbatical period as a Research Staff Member at IBM's T.J. Watson Research Center.