- Work
- » Speculative Parallelization & Chip Multiprocessor
- iWatcher: Efficient Architectural Support for Software Debugging
by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
31th Annual International Symposium on Computer Architecture (ISCA), June 2004.
- Speculative Synchronization
by Jose Martinez and Josep Torrellas,
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2003.
- Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003.
- ReEnact: Using Thread-Level Speculation to Debug Data Races in Multithreaded Codes
by Milos Prvulovic and Josep Torrellas,
30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
- Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
9th International Symposium on High-Performance Computer Architecture (HPCA), February 2003.
- Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
by José F. Martínez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas,
35th International Symposium on Microarchitecture (MICRO), November 2002.
- Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications
by José F. Martínez and Josep Torrellas,
10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
- Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
by Marcelo Cintra and Josep Torrellas,
Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002.
- Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
by Milos Prvulovic, Maria Jesus Garzaran, Lawrence Rauchwerger, and Josep Torrellas,
28th Annual International Symposium on Computer Architecture (ISCA), June 2001.
- Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors
by José F. Martínez and Josep Torrellas,
Workshop on Memory Performance Issues, June 2001.
- Software Logging under Speculative Parallelization
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
Workshop on Memory Performance Issues, June 2001.
- The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
by Venkata Krishnan and Josep Torrellas,
International Journal of Parallel Processing (IJPP), Vol. 29, Number 1, pp. 3-33, February 2001.
A shorter version of this paper appeared in International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999.
- Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems
by Marcelo Cintra, José F. Martínez and Josep Torrellas,
27th Annual International Symposium on Computer Architecture (ISCA), June 2000.
(Presentation slides)
- Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
Fifth International Symposium on High-Performance Computer Architecture (HPCA), January 1999.
- Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
First Workshop on Parallel Computing for Irregular Applications, held in conjunction with HPCA-5, January 1999.
- Hardware for Speculative Parallelization in High-End Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
The Third PetaFlop Workshop (TPF-3), February 1999.
- Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998.
- A Chip Multiprocessor Architecture with Speculative Multithreading
by Venkata Krishnan and Josep Torrellas,
IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999.
- Software Trace Cache
by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero,
1999 ACM International Conference on Supercomputing (ICS), June 1999.
- Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor
by Venkata Krishnan and Josep Torrellas,
International Conference on Supercomputing (ICS), July 1998.
- Executing Sequential Binaries on a Multithreaded Architecture with Speculation Support
by Venkata Krishnan and Josep Torrellas,
Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98), January 1998.
- A Clustered Approach to Multithreaded Processors
by Venkata Krishnan and Josep Torrellas,
International Parallel Processing Symposium (IPPS), March 1998.
- Efficient Use of Processing Transistors for Larger On-Chip Storage: Multithreading
by Venkata Krishnan and Josep Torrellas,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997.