- Work
- » Low Power Design
- Managing Multiple Low-Power Adaptation Techniques: The Positional Approach
by Michael Huang, Jose Renau and Josep Torrellas,
Sidebar, Special Issue on Power-Aware Computing, IEEE Computer, December 2003. - Positional Adaptation of Processors: Application to Energy Reduction
by Michael Huang, Jose Renau, and Josep Torrellas,
30th Annual International Symposium on Computer Architecture (ISCA), June 2003. - Energy-Efficient Hybrid Wakeup Logic
by Michael Huang, Jose Renau, and Josep Torrellas,
International Symposium on Low Power Electronics and Design (ISLPED), August 2002. - Profile-Based Energy Reduction for High-Performance Processors
by Michael Huang, Jose Renau, and Josep Torrellas,
Fourth Workshop on Feedback Directed and Dynamic Optimization (FDDO), December 2001. - The Design of DEETM: A Framework for Dynamic Energy Efficiency and Temperature Management
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
Journal of Instruction-Level Parallelism (JILP), Vol. 3, October 2001.
A shorter version appeared as
A Framework for Dynamic Energy Efficiency and Temperature Management
33rd International Symposium on Microarchitecture (MICRO), December 2000. - L1 Data Cache Decomposition for Energy Efficiency
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
International Symposium on Low Power Electronics and Design (ISLPED), August 2001. - A Framework for Dynamic Energy Efficiency and Temperature Management
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
33rd International Symposium on Microarchitecture (MICRO), December 2000.
The power model used is discussed in CSRD Technical Report 1584, October 2000.