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  1. High Performance Memory Systems
    by Haldun Hadimioglu, David Kaeli, Jeff Kuskin, Ashwini Nanda and Josep Torrellas, editors
    290 pages, ISBN: 0-387-00310-X, Springer Verlag, New York, 2003.

  2. Design Trade-offs in High-Throughput Coherence Controllers
    by Anthony Nguyen and Josep Torrellas,
    International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003.

  3. ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
    by Milos Prvulovic, Zheng Zhang, and Josep Torrellas
    29th Annual International Symposium on Computer Architecture (ISCA), May 2002.

  4. Compiler-Assisted Software and Hardware Support for Reduction Operations
    by F. Dang, M. Garzaran, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger, and J. Torrellas,
    NSF Workshop on Next Generation Systems, April 2002.

  5. Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors
    by Maria Jesus Garzaran, Milos Prvulovic, Alin Jula, Hao Yu, Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas
    International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001.

  6. Cache-Only Memory Architectures
    by Fredrik Dahlgren and Josep Torrellas,
    IEEE Computer Magazine, June 1999.

  7. Improving the Performance of Bristled CC-NUMA Systems Using Virtual Channels and Adaptivity
    by José F. Martínez, Josep Torrellas, and Jose Duato,
    1999 ACM International Conference on Supercomputing (ICS), June 1999.

  8. Excel-NUMA: Toward Programmability, Simplicity, and High Performance
    by Zheng Zhang, Marcelo Cintra, and Josep Torrellas,
    IEEE Transactions on Computers, Special Issue on Cache Memory, February 1999.
    A longer version is CSRD Technical Report 1544, November 1996.

  9. Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability
    by Josep Torrellas,
    9th SIAM Conference on Parallel Processing for Scientific Computing, March 1999.

  10. Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
    by Sujoy Basu and Josep Torrellas,
    Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998.

  11. The Performance of the Cedar Multistage Switching Network
    by Josep Torrellas and Zheng Zhang,
    IEEE Transactions on Parallel and Distributed Systems, April 1997.
    A shorter version appeared as
    The Performance of the Cedar Multistage Switching Network
    Supercomputing'94, November 1994.

  12. Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA
    by Zheng Zhang and Josep Torrellas,
    Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997.

  13. Speeding up the Memory Hierarchy in Flat COMA Multiprocessors
    by Liuxi Yang and Josep Torrellas,
    Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997.

  14. The Illinois Aggressive Coma Multiprocessor Project (i-acoma)
    by Josep Torrellas and David Padua,
    6th Symposium on the Frontiers of Massively Parallel Computing, October 1996.

  15. An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors
    by Manuel Perez Malumbres(*), Jose Duato(*), and Josep Torrellas,
    (* Universidad Politecnica de Valencia). 1996 Symposium on Parallel and Distributed Processing (SPDP), October 1996.

  16. Optimizing the Primary Cache for Parallel Scientific Applications: The Pool Buffer Approach
    by Liuxi Yang and Josep Torrellas,
    1996 International Conference on Supercomputing (ICS), June 1996.

  17. Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors
    by Alain Raynaud, Zheng Zhang, and Josep Torrellas,
    Second International Symposium on High-Performance Computer Architecture (HPCA), January 1996.

  18. Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors,
    by Josep Torrellas, Andrew Tucker and Anoop Gupta,
    Journal of Parallel and Distributed Computing, February 1995.

  19. The Performance of the Cedar Multistage Switching Network
    by Josep Torrellas and Zheng Zhang,
    Supercomputing'94, November 1994.

  20. An Efficient Algorithm for the Run-time Parallelization of DOACROSS Loops
    by Ding-Kai Chen, Josep Torrellas and Pen-Chung Yew,
    Supercomputing'94, November 1994.

  21. Comparing the Performance and Programmibility of the DASH and Cedar Multiprocessors for Scientific Loads
    by Josep Torrellas and David Koufaty, and David Padua,
    1994 International Conference on Parallel Processing (ICPP), August 1994.

  22. False Sharing and Spatial Locality in Multiprocessor Caches,
    by Josep Torrellas, Monica S. Lam and John L. Hennessy,
    Transactions on Computers, June 1994.

  23. Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System,
    by Josep Torrellas, Anoop Gupta, and John Hennessy,
    ASPLOS V, October 1992.