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The FlexRAM architecture proposes to replace traditional memory chips with more advanced Intelligent Memory Chips. A FlexRAM chips has 64 nodes, each one has a simple processor attached to 1MByte of DRAM.

All the latency, energy consumption, and area parameters have been calculated using a 0.18um MLD from IBM. A detailed architecture description could be found in the Publications section.

The architecture has evolve from the first publication (ICCD99). It has been tuned for performance and energy considerations. The main differences with the ICCD paper are the following:

The inclusion of a sizable cache, around 8KBytes per node.
Use only one Row Buffer per memory bank.
Increase the PArray issue from single issue to double issue. 

The energy consumption calculation has been refined with the time. The first evaluations were based in the worst case. The second version were calculated with scale down theory over similar processors. This version included a different energy consumption for each block in the FlexRAM architecture. Currently we are designing the floor plan obtaining more realistic H-SPICE which considers transient consumption.



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Last modified: September 10, 2000