• Papers
    • » Hardware Reliability and Variability
  1. Extreme-Scale Computer Architecture
    by Josep Torrellas,
    National Science Review, Special Issue on High Performance Computing, Oxford University Press, 2015.

  2. Many-Core Architecture for NTC: Energy Efficiency from the Ground Up
    by Josep Torrellas,
    Near Threshold Computing - Technology, Methods and Applications, Michael Huebner and Cristina Silvano Editors, Springer, 2015.

  3. Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules
    by Aditya Agrawal, Amin Ansari, and Josep Torrellas,
    International Symposium on High Performance Computer Architecture (HPCA), February 2014. [Presentation slides]

  4. Coping with Parametric Variation at Near-Threshold Voltages
    by Ulya Karpuzcu, Nam Sung Kim, and Josep Torrellas,
    IEEE Micro Magazine, Special Issue on Reliability-Aware Microarchitecture Design, Volume:33 Issue:4, July-Aug. 2013.

  5. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages
    by Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim and Josep Torrellas,
    International Conference on Dependable Systems and Networks (DSN), June 2012. [Presentation slides]

  6. LeadOut: Composing Low-Overhead Frequency-Enhancing Techniques for Single-Thread Performance in Configurable Multicores
    by Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas,
    16th International Symposium on High-Performance Computer Architecture (HPCA), January 2010. [Presentation slides]

  7. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration
    by Ulya R. Karpuzcu, Brian Greskamp and Josep Torrellas,
    International Symposium on Microarchitecture (MICRO), December 2009. Best Paper Award. [Presentation slides]

  8. BubbleWrap: Popping CMP Cores for Sequential Acceleration
    by Brian Greskamp, R. Ulya Karpuzcu, and Josep Torrellas,
    Wild and Crazy Ideas Session, at 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009. Best Idea Award. [Presentation slides]

  9. BlueShift: Designing Processors for Timing Speculation from the Ground Up
    by Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles,
    15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009. [Presentation slides]

  10. Techniques to Mitigate the Effects of Congenital Faults in Processors
    by Smruti R. Sarangi and Josep Torrellas
    160 pages, ISBN: 978-3-639-04637-3, VDM Verlag, 2008.

  11. Facelift: Hiding and Slowing Down Aging in Multicores
    by Abhishek Tiwari and Josep Torrellas,
    41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides]

  12. EVAL: Utilizing Processors with Variation-Induced Timing Errors
    by Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas,
    41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides]

  13. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
    by Radu Teodorescu and Josep Torrellas,
    35th Annual International Symposium on Computer Architecture (ISCA), June 2008. [Presentation slides]

  14. An Updated Evaluation of ReCycle
    by Abhishek Tiwari and Josep Torrellas,
    7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides]

  15. Using Register Lifetime Predictions to Protect Register Files Against Soft Errors
    by Pablo Montesinos, Wei Liu, and Josep Torrellas,
    IEEE Transactions on Dependable and Secure Computing (IEEE TDSC), To Appear, 2008.

  16. OpenSPARC: An Open Platform for Hardware Reliability Experimentation
    by Ishwar Parulkar, Alan Wood, James C. Hoe, Babak Falsafi, Sarita Adve, Josep Torrellas, and Subhasish Mitra,
    Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2008. [Presentation slides]

  17. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
    by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
    IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008. [Presentation slides]

  18. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
    by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
    40th International Symposium on Microarchitecture (MICRO), December 2007. [Presentation slides]

  19. Estimating Design Time for System Circuits
    by Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau,
    International Conference on Very Large Scale Integration (VLSI-SoC), October 2007.

  20. ReCycle: Pipeline Adaptation to Tolerate Process Variation
    by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas,
    34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [Presentation slides]
    An updated version with a more realistic pipeline model appears in An Updated Evaluation of ReCycle
    by Abhishek Tiwari and Josep Torrellas,
    7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides]

  21. VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects
    by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas,
    Workshop on Architectural Support for Gigascale Integration (ASGI), June 2007.

  22. Using Register Lifetime Predictions to Protect Register Files Against Soft Errors
    by Pablo Montesinos, Wei Liu, and Josep Torrellas,
    37th International Conference on Dependable Systems and Networks (DSN), June 2007. [Presentation slides]
    This is an extension of Shield: Cost-Effective Soft-Error Protection for Register Files
    Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006. [Presentation slides]

  23. Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
    by Brian Greskamp, Smruti Sarangi, and Josep Torrellas,
    International Symposium on Circuits and Systems (ISCAS),
    Special Session: Circuit Design in the Presence of Device Variability, May 2007. [Presentation slides]

  24. A Model for Timing Errors in Processors with Parameter Variation
    by Smruti Sarangi, Brian Greskamp, and Josep Torrellas,
    8th International Symposium on Quality Electronic Design (ISQED), March 2007.

  25. Patching Processor Design Errors with Programmable Hardware
    by Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, and Josep Torrellas,
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2007.

  26. Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
    by Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas,
    39th International Symposium on Microarchitecture (MICRO06), December 2006. Best Paper Award. [Presentation slides]

  27. Shield: Cost-Effective Soft-Error Protection for Register Files
    by Pablo Montesinos, Wei Liu, and Josep Torrellas,
    Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC206), October 2006. [Presentation slides]

  28. Designing Hardware that Supports Cycle-Accurate Deterministic Replay
    by Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas,
    Workshop on Complexity-Effective Design (WCED), June 2006.

  29. CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
    by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
    International Conference on Dependable Systems and Networks (DSN), June 2006. [Presentation slides]