VARIUS: A model of within-die process variation and resulting
timing errors in manycores for microarchitects.
Process variation poses a major challenge to
high-performance processor design, negatively
impacting a processor's frequency and leakage power.
To study the impact of variation, as well as to stimulate the
development of microarchitectural solutions to reduce its
impact, we developed a microarchitecture-level model for
process variation and its resulting timing errors in processors.
NEW (June 2012): We recently extended the VARIUS model to apply to Near
Threshold Voltage Computing. We call it VARIUS-NTV.
Please find the VARIUS-NTV
model here
A paper that describes the model is:
VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity
of Manycores to Process Variations at Near-Threshold Voltages
by Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim and Josep Torrellas,
International Conference on Dependable Systems and Networks (DSN),
June 2012.
[Presentation slides]
The original VARIUS model, which applies to conventional, super-threshold
voltage computing can be
dowloaded from here.
The two papers that describe the model are:
VARIUS: A Model of Process Variation and Resulting Timing Errors
for Microarchitects
by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano,
Abhishek Tiwari and Josep Torrellas,
IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008.
[Presentation slides]
VARIUS: A Model of Parameter Variation and Resulting Timing Errors
for Microarchitects
by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi,
Abhishek Tiwari and Josep Torrellas,
Workshop on Architectural Support for Gigascale Integration (ASGI), June 2007.
Some papers that use the model are:
Variation-Aware Application Scheduling and Power Management for Chip
Multiprocessors
by Radu Teodorescu and Josep Torrellas,
35th Annual International Symposium on Computer Architecture (ISCA), June 2008.
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
40th International Symposium on Microarchitecture (MICRO), December 2007.
ReCycle: Pipeline Adaptation to Tolerate Process Variation
by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas,
34th Annual International Symposium on Computer Architecture (ISCA), June 2007.
If you have any questions about VARIUS, please
let us know.
If you download VARIUS, please
send us a mail. We intend to create a mailing list to keep you
updated on future releases.
Last modified
July 2012
by
Josep Torrellas (torrellas@cs.uiuc.edu)