The i-acoma group at UIUC

Pablo Montesinos Ortego

Research Interests:

Computer architecture, multicore and parallel architectures, support for deterministic replay of parallel execution, programmability, chunk-based execution and transactional memory. Gazpacho, etc...

Publications:

Multicore Architectures and Deterministic Replay

• Derek H. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas, "Two Hardware-based Approaches for Deterministic Multiprocessor Replay". Research Highlight, Communications of the ACM (CACM). To appear, 2009. (Authors in alphabetical order).
• Pablo Montesinos, Matthew Hicks, Samuel T. King and Josep Torrellas,
  "Capo: Abstractions and Software-Hardware Interface for Hardware-Assisted Deterministic Multiprocessor Replay". 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009.
• Pablo Montesinos, Luis Ceze and Josep Torrellas, " DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently". 35th Annual International Symposium on Computer Architecture (ISCA), June 2008.
• Luis Ceze, James Tuck, Pablo Montesinos and Josep Torrellas, "Bulk Enforcement of Sequential Consistency", Proceedings of the Thirty-fourth Annual International Symposium on Computer Architecture (ISCA), June 2007.

Programmability and Data Centric Sychronization

• Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos and Josep Torrellas "Concurrency Control with Data Coloring" . MSPC 2008: ACM SIGPLAN Workshop on Memory Systems Performance and Correctness. March 2008.
• Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas, "Colorama: Architectural Support for Data-Centric Synchronization" . Appears in the 13th International Symposium on High Performance Computer Architecture (HPCA). February 2007.

Processor and System Reliability

• Pablo Montesinos, Wei Liu and Josep Torrellas, "Using Register Lifetime Predictions to Protect Register Files Against Soft Errors". This is an extended version of the DSN 2007 paper, and has been submitted as an invited paper to an IEEE Journal, February 2008.
• Pablo Montesinos, Wei Liu and Josep Torrellas, "Using Register Lifetime Predictions to Protect Register Files Against Soft Errors". Proceedings of the Thirty-seventh Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2007), June 2007.
• Pablo Montesinos, Wei Liu, Josep Torrellas, "Shield: Cost-Effective Soft-Error Protection for Register Files" .

  Appears in the Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC206). October 2006.

• Jun Nakano, Pablo Montesinos, Josep Torrellas, "Efficient Handling of I/O in Highly-Available Rollback Recovery Servers" .Appears in the 12th International Symposium on High Performance Computer Architecture (HPCA). February 2006.

Other Papers and Software

• Pablo Montesinos, "Stage Driver". Appears in The 12th Pattern Languages of Programs (PLoP). August 2005.
• Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvlovic, Luis Ceze, Smruti Sarangi, Paul Sack, Karin Strauss and Pablo Montesinos. "SESC Simulator"

Academic Stuff:

Here are some papers that I worked on for some of my classes at UIUC. Don't expect to find anything incredible, though.

• "iPoJ: User-Space Sandboxing for Linux 2.4" . cs598CZ.
• "Enhanching MLP: A Survey of Runahead Execution and Related Techniques" . cs598CZ.

Contact Information

Pablo Montesinos
4238, Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin.
Urbana, IL. 61801-2302.
Phone (217) 244-2445, fax 217-265-6582.
E-mail: pmontesi-EN-uiuc.edu.
Homepage: here