Professor Josep Torrellas
Director, SRC/DARPA JUMP 2.0 ACE Center for Evolvable Computing
Saburo Muroga Professor of Computer Science, University of Illinois at Urbana-Champaign
( Google Scholar, CV January 2024

Looking for Graduate Students:

The SRC/DARPA JUMP 2.0 ACE Center for Evolvable Computing has started in January 2023. This 5-year 21-Principal Investigator project is focused on transforming distributed computing, substantially improving its energy efficiency and performance. See the Official Announcement, as well as the SRC announcements (here and here) and the DARPA announcement. I am looking for graduate students who want to get involved in the Center. It is a great opportunity for individuals who are looking to learn and perform research on cross-disciplinary issues in computing systems, interact with students and senior researchers across the community, and have a close collaboration with computer industry leaders. If interested, please send an email with your CV to


Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He is the Director of the SRC/DARPA JUMP 2.0 ACE Center for Evolvable Computing, past Co-Leader of an Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC).

Torrellas has made contributions to shared-memory multiprocessor architectures and thread-level speculation (TLS) over more than thirty years. He was the first to apply TLS ideas to parallel architectures and programs: He used speculative multithreading to eliminate stalling due to synchronization (Speculative Synchronization), identify and debug data races (ReEnact), monitor memory accesses (I-Watcher), provide fault tolerance (ReVive), and inexpensively enforce sequential consistency (BulkSC). Some of these ideas impacted IBM's Blue Gene and other commercial machines. Torrellas was part of the design team of IBM’s PERCS Multiprocessor, an architecture for productivity. The team considered some of his TLS mechanisms, as well as processing-in-memory features inspired by his FlexRAM Intelligent Memory project.

Using mechanisms inspired by TLS, Torrellas developed the Bulk Architecture, an out-of-the-box scalable shared-memory multiprocessor for programmability that was influential within Intel as part of the Illinois-Intel Parallelism Center. Torrellas also applied TLS ideas to develop Record and deterministic Replay (RnR) architectures and, together with Intel, he built QuickRec, the first RnR hardware prototype, which used FPGAs to extend Intel’s cores and caches for RnR.

Torrellas has made contributions to multiprocessor architectures, NUMA organizations, cache coherence protocols, hardware synchronization, and prefetching schemes. In recognition, the government made his I-ACOMA multiprocessor one of the Ten Design-Point Studies funded nationwide to attain Petaflop machines. He was involved in the Stanford DASH and Illinois Cedar experimental multiprocessors. His early work on false sharing and cache behavior of OS and commercial workloads influenced compiler writers and architects of early parallel machines, such as the Silicon Graphics Origin2000. Torrellas was also co-leader of the Intel Runnemede Extreme-Scale multiprocessor, a machine designed for energy efficiency that impacted Intel’s high-end architectures.

Torrellas received the 2021 IEEE Computer Society Harry H. Goode Memorial Award ”for contributions to energy efficient and programmable shared-memory multiprocessor architectures”, the 2017 UIUC Campus Award for Excellence in Graduate Student Mentoring, and the 2015 IEEE Computer Society Technical Achievement Award ”for pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation”. He has received a Google Faculty Research Award, IBM Partnership Awards, Intel Research Council Awards, and an NSF Young Investigator Award. He was a Willett Faculty Scholar at Illinois (2002-9). He is a Fellow of IEEE, ACM, and AAAS. He has received many Best Paper Awards and a High-Impact Paper Award.

Torrellas has mentored generations of computer architects. Of his 48 Ph.D. graduates, over a dozen are faculty at top US academic institutions, including Martínez (Cornell), Solihin (UCF), Huang (Rochester), Prvulovic (Gatech), Renau (UCSC), Tuck (NCSU), Ceze (Washington), Teodorescu (OSU), Ahn (Pittsburgh), Muzahid (Texas A&M), Karpuzcu (Minnesota), Qian (Purdue), Honarmand (Stony Brook), Yan (MIT), and Skarlatos (CMU).

Torrellas has served as the Chair of the IEEE CS Technical Committee on Computer Architecture (TCCA) (2018-22). He has also served in the Board of Directors of the Computing Research Association (CRA) (2016-19), has been a Council Member of CRA’s Computing Community Consortium (CCC) (2011-14), and has served as a Member of the U.S. National Academies Board on Army Research and Development (2018-23). He currently serves in the International Roadmap for Devices and Systems (IRDS). He has co-organized many funding and visioning workshops. His workshops on Advancing Computer Architecture Research helped usher NSF’s XPS Program.

Prior to being at UIUC, Torrellas received a Ph.D. from Stanford University.

Recent News (whole list at the News Tab):

Torrellas leads The i-acoma Architecture Group, which focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. Two examples of projects we have done in the past:

Examples of Architectures We Designed in the Past:

Some Recent Publications:

Software Released:

  • VARIUS and VARIUS-NTV: A model of within-die process variation and resulting timing errors in manycores for microarchitects.
  • SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.

Emphasis Research Areas:

The main emphasis research areas in the group are:

Currently Teaching:

CS533: Parallel Computer Architectures.

Contact Information

Josep Torrellas
4231 Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 244-4148, fax 217-265-6582.

Administrative Assistant

Madeleine Garvey,
Thomas M. Siebel Center for Computer Science.
University of Illinois.
201 N. Goodwin Ave.
Urbana, IL. 61801.
Phone (217) 300-6342.

Our research is funded by NSF, DARPA, and DOE.