
CV OF JOSEP TORRELLAS (PDF VERSION here) January 2024.
Education
Experience
Honors and Awards
Main Professional Society Service
Designed Architectures
Distributed Software
Graduated Ph.D. Students
Publications
Patents
Editorship of Journals
Recent Research Funding
Invited Lectures
Conference Organization. Steering Committee
Conference Organization. Chair
Conference Organization. Program Committee
Workshop Organization. Chair
Workshop Organization. Program Committee
Tutorials and Short Courses
Panels Organized
Participation in Panels
Talks at Workshops
Participation in Other Workshops and Meetings
Postdoctoral Researchers, M.S. Students, and Visitors
Teaching Activity
Other Major Service Outside UIUC
Major Service Inside UIUC
Other Activities
Education
- Ph.D. Electrical Engineering, Stanford University, 1992.
Dissertation: "Multiprocessor Cache Memory Performance: Characterization and Optimization".
Advisor: John Hennessy. - M.S. Electrical and Computer Engineering, University of Wisconsin-Madison, 1987.
- B.S. Electrical Engineering, Universitat Politecnica de Catalunya, 1986.
Experience
- Director, SRC/DARPA JUMP 2.0 ACE Center for Evolvable Computing, January 2023 - pres.
- Saburo Muroga Professor of Computer Science, University of Illinois at Urbana-Champaign (UIUC), January 2016 - pres.
- Professor, Coordinated Science Laboratory (CSL), UIUC, August 2020 - pres.
- Director, Center for Programmable Extreme-Scale Computing, UIUC, January 2011 - December 2022.
- Co-Leader, Intel Strategic Research Alliance (ISRA) Center on Computer Security, UIUC, June 2018 - June 2021.
- Director, Illinois-Intel Parallelism Center (I2PC), UIUC, September 2011 - September 2013.
- Researcher, Information Trust Institute (ITI), UIUC, January 2006 - pres.
- Professor, Computer Science Department, UIUC, August 2002 - pres.
- Willett Faculty Scholar, Computer Science Dept., UIUC, August 2002 - August 2009.
- Leader, University of Illinois OpenSPARC Center of Excellence, UIUC, September 2007 - August 2010.
- Computer Architecture Leader, Universal Parallel Computing Research Center (UPCRC), UIUC, February 2008 - August 2011.
- Associate Professor, Computer Science Department, UIUC, August 1998 - August 2002.
- Research Staff Member, IBM T.J. Watson Research Center, IBM Research (sabbatical period), May 1998 - January 1999.
- Departmental Affiliate, Electrical and Computer Engineering Department, UIUC, April 1993 - pres.
- Assistant Professor, Computer Science Department, UIUC, August 1992 - August 1998.
- Senior Computer Systems Engineer, Center for Supercomputing Research and Development (CSRD), UIUC, August 1992 - December 1996.
Honors and Awards
- 2025 The paper "Untangle" is selected in Top Picks in Hardware and Embedded Security in 2024.
- 2024 Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, College of Engineering, UIUC.
- 2024 One paper in the 2024 IEEE Micro Top Picks from Computer Architecture Conferences ("Micro-Armed Bandid") and three Honorable Mention papers ("μManycore", "SPADE", and "Everywhere All at Once").
- 2023 IEEE Computer Society Golden Core Member.
- 2023 Paper "Bulk Disambiguation of Speculative Threads in Multiprocessors" (ISCA 2006) selected for the Collection of Retrospectives on Selected Papers from the Second 25 Years of ISCA.
- 2022 Two papers in the 2022 IEEE Micro Top Picks from Computer Architecture Conferences.
- 2021 First Prize, Intel Hardware Security Academic Award, for the paper "Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution".
- 2021 IEEE Computer Society Harry H. Goode Memorial Award. For "Contributions to energy efficient and programmable shared-memory multiprocessor architectures".
- 2021 In List of Teachers Ranked as Excellent by their Students: Spring 2021.
- 2021 One Selected paper and one Honorable Mention paper in 2021 IEEE Micro Top Picks from Computer Architecture Conferences.
- 2020 Upstreamed to Linux 5.11 the Draco System Call checking software.
- 2020 Best Paper Award, International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020.
- 2020 Two Selected papers and one Honorable Mention paper in 2020 IEEE Micro Top Picks from Computer Architecture Conferences.
- 2020 Google Faculty Research Award.
- 2020 Keynote at the 2020 HPCA/PPoPP/CGO conferences.
- 2020 Research Highlight paper in Communications of the ACM (CACM).
- 2020 Cover article in IEEE Control Systems Magazine.
- 2019 In List of Teachers Ranked as Excellent by their Students: Spring 2019 and Fall 2019.
- 2019 Best Paper Award, 52nd International Symposium on Microarchitecture (MICRO), October 2019.
- 2019 Honorable Mention in 2019 IEEE Micro's Top Picks from Computer Architecture Conferences.
- 2018 Co-leader, Intel Strategic Research Alliance (ISRA) Center on Computer Security.
- 2018 In List of Teachers Ranked as Excellent by their Students: Spring 2018 and Fall 2018.
- 2017 Best Paper Nominee, International Conference on Parallel Architectures and Compilation Techniques (PACT).
- 2017 University of Illinois at Urbana-Champaign Campus Award for Excellence in Graduate Student Mentoring.
- 2016 Fellow of the American Association for the Advancement of Science (AAAS).
- 2016 Member of the Board of Directors (Elected), Computing Research Association (CRA).
- 2016 Saburo Muroga Professorship of Computer Science, UIUC.
- 2015 IEEE Computer Society Technical Achievement Award, for "Pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation".
- 2015 Honorable Mention Paper, IEEE Micro Special Issue: 2015 Micro's Top Picks from Computer Architecture Conferences.
- 2014 Distinguished Paper Award, International Conference on Programming Language Design and Implementation (PLDI), June 2014.
- 2014 Best Paper Award Finalist, International Symposium on High Performance Computer Architecture (HPCA), February 2014.
- 2013 Distinguished Speaker Award, IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP), June 2013.
- 2012 High-Impact Paper Award, International Conference on Computer Design (ICCD), October 2012. For "One of the 5 most cited papers in the first 30 years of ICCD (1983-2012)".
- 2012 Jon Postel Distinguished Lecturer, Computer Science Department, UCLA, November 2012.
- 2010 ACM Fellow.
- 2009 Best Paper Award, 42nd International Symposium on Microarchitecture (MICRO), December 2009.
- 2009 Paper in IEEE Micro Special Issue: 2009 Micro's Top Picks from Computer Architecture Conferences.
- 2009 Research Highlight paper in Communications of the ACM (CACM).
- 2009 Best Idea Award, Wild and Crazy Ideas Session, at International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009.
- 2007 Paper in IEEE Micro Special Issue: 2007 Micro's Top Picks from Computer Architecture Conferences.
- 2006 Best Paper Award, 39th International Symposium on Microarchitecture (MICRO), December 2006.
- 2006 Paper in IEEE Micro Special Issue: 2006 Micro's Top Picks from Computer Architecture Conferences.
- 2004 Paper in IEEE Micro Special Issue: 2004 Micro's Top Picks from Computer Architecture Conferences.
- 2004 IEEE Fellow.
- 2003 Paper in IEEE Micro Special Issue: 2003 Micro's Top Picks from Computer Architecture Conferences.
- 2002-2009 Willett Faculty Scholar, UIUC.
- 2001 Best Paper Award, Fifth Workshop on Multithreaded Execution, Architecture, and Compilation.
- 2000 Senior Xerox Award for Outstanding Faculty Research, UIUC.
- 1997-00 IBM Partnership Award.
- 1997 C. W. Gear Outstanding Junior Faculty Award, UIUC.
- 1997 Junior Xerox Award for Outstanding Faculty Research, UIUC.
- 1995,6,8 Intel Research Council Award.
- 1994-9 National Science Foundation Young Investigator Award.
- 1993-6 National Science Foundation Research Initiation Award.
Main Professional Society Service
- Chair, The Institute of Electrical and Electronics Engineers (IEEE) Technical Committee on Computer Architecture (TCCA), November 2018 - December 2022. Main activities included:
- Help organize and fund about 10 technical conferences yearly.
- Promote the careers of members.
- Co-ordinate many activities for the betterment of the computer architecture community.
- Provide funds for students to travel to conferences.
- Serve in the Steering Committee of conferences.
- Member of the Executive Committee, IEEE TCCA, October 2010 - 2018 and 2023 - present.
- Member, U.S. National Academies Board on Army Research and Development, May 2018 - May 2023.
- Co-organizer, workshops on "Machine Learning and High-Performance Computing", May 2020 and August 2020.
- Co-organizer, NSF Visioning Workshop on "Inter-Disciplinary Research Challenges in Computer Systems for the 2020s", Williamsburg, VA, March 2018. Workshop produced a Report that was handed over to NSF and was published in the ACM Digital Library.
- Member, International Roadmap for Devices and Systems (IRDS) Applications Benchmarking Focus Team, September 2016 - pres. This is the successor of the International Technology Roadmap for Semiconductors.
- Member, Board of Directors, Computing Research Association (CRA), July 2016 - June 2019. Main activities included:
- Co-lead an initiative to improve computer science faculty recruiting by creating an on-line CRA database of faculty candidates.
- Co-organize a session on "Improving Faculty Recruiting in the Computing Community", in the 2018 Conference at Snowbird, July 2018.
- Attendee, Leadership in Science Policy Institute Workshop, Computing Community Consortium (CCC), Washington DC, April 2015.
- Council Member, The Computing Community Consortium (CCC), CRA. January 2011 - June 2014. Main activities included:
- Member of the Subcommittee on Visioning Activities.
- Laision for a visioning workshop by the design automation community.
- Chair and co-editor, "SIGARCH/TCCA's Recommended Best Practices for ISCA Program Chairs", June 2013.
- Co-editor, CCC Visioning white paper: "21st Century Computer Architecture, A Community White Paper", May 2012.
- Chair, IEEE TCCA, July 2005 - October 2010. Main accomplishments included:
- Successfully co-located ACM PPoPP and IEEE HPCA for interdisciplinary interactions.
- Created the HPCA Hall of Fame and the HPCA Conference Repository.
- Created the HPCA conference Industrial Session.
- Distributed hard copies of HPCA proceedings.
- Co-organizer of two CCC Visioning Workshops on Advancing Computer Architecture Research: "Failure is not an Option: Popular Parallel Programming" and "What Now in ILP Research?", both in 2010.
- Participant in the CRA Visioning workshop: "Revitalizing Computer Architecture Research", December 2005.
- Vice-Chair and Member of the Advisory Board, IEEE TCCA, 1998 - July 2005.
Designed Architectures
- "QuickRec: A Hardware Prototype for Recording and Deterministically Replaying Multithreaded Programs in the Intel Architecture". This prototype has been developed in collaboration with Intel, and is described in the QuickRec ISCA-2013 paper.
- "Runnemede: An Chip Multiprocessor for Extreme-Scale Computing". This manycore chip has been designed in collaboration with Intel, and is described in the Runnemede HPCA-2013 paper.
Distributed Software
- "DRACO: A Linux Patch to Speed-up System Call Checking". This is a patch in the official Linux distribution that checks system calls for security. It is based on our Draco paper. December 2020.
- "VARIUS and VARIUS-NTV: A Model of Process Variation". This tool models within-die process variation and the resulting timing errors in manycores at a level suitable for microarchitects. June 2007.
- "SESC: A Simulator of Superscalar Multiprocessors and Memory Systems with Thread-Level Speculation Support". SESC is a multiprocessor simulator package with support for thread-level speculation. June 2005.
- "Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors". Scal-Tool is a public-domain tool that is available through the NCSA software repository. May 1999.
- "Augmint: A Multiprocessor Simulation Environment for Intel x86 Architectures". Augmint is a multiprocessor tracing and evaluation package that runs on Intel x86 machines. December 1995.
Graduated Ph.D. Students
- Graduated 48 Ph.D. Students (15 are Faculty at Top US Universities):
- Serif Yesil, 2022. First Job: Member of Technical Staff, Nvidia, Santa Clara, CA. Thesis: "Processing Graphs and Sparse Matrices Efficiently".
- Apostolos Kokolis, 2022. First Job: Member of Technical Staff, Meta, Seattle, WA. Thesis: "New Architectures for Non-Volatile Memory Technologies". David J. Kuck Outstanding PhD Thesis Award. Also, thesis selected to represent the CS department in the ACM PhD Thesis Award competition.
- Zhangxiaowen (Andy) Gong, 2021. First Job: Member of Technical Staff, Intel, Santa Clara, CA. Thesis: "Exploiting and Coping with Sparsity to Accelerate DNNs on CPUs".
- Antonio Maria Franques Garcia, 2021. First Job: Member of Technical Staff, Apple, Cupertino, CA. Thesis: "On-Chip Wireless Manycore Architectures".
- Azin Heidarshenas, 2021. First Job: Member of Technical Staff, Apple, Cupertino, CA. Thesis: "Speeding-up Graph Processing on Shared-Memory Platforms by Optimizing Scheduling and Compute".
- Dimitrios Skarlatos, 2020. First Job: Assistant Professor, Department of Computer Science, Carnegie Mellon University, Pittsburgh, PA. Thesis: "Rethinking Computer Architecture and Operating System Abstractions for Good and Evil". David J. Kuck Outstanding PhD Thesis Award. Also, 2021 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. Also, thesis selected to represent the CS department in the ACM PhD Thesis Award competition.
- Raghavendra Pradyumna Pothukuchi, 2020. First Job: Postdoctoral Researcher, Department of Computer Science, Yale University, New Haven, CT. CIFellow 2021-23. Thesis: "Intelligent Systems for Efficiency and Security".
- Thomas Shull, 2020. First Job: Senior Member of Technical Staff, Oracle Labs, Zurich, Switzerland. Thesis: "Making Non-Volatile Memory Programmable".
- Yasser Shalabi, 2020. First Job: Symmetry Systems. Thesis: "Leveraging Concurrency for Performance and Security".
- Mengjia Yan, 2019. First Job: Assistant Professor, Department of Electrical Engineering and Computer Science, MIT, MA. Thesis: "Cache-Based Side Channels: Modern Attacks and Defenses". David J. Kuck Outstanding PhD Thesis Award. Honorable Mention of the 2020 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. Thesis selected to represent the CS department in the ACM PhD Thesis Award competition.
- Bhargava Gopireddy, 2018. First Job: Nvidia, Santa Clara, CA. Thesis: "Energy Efficient Core Designs For Upcoming Process Technologies".
- Jiho Choi, 2018. First Job: Google, Mountain View, CA. Thesis: "HW-SW Co-Design Techniques For Modern Programming Languages".
- Wooil Kim, 2015. First Job: Member of Technical Staff, Samsung Electronics, Seoul, Korea. Thesis: "Architecting, Programming, and Evaluating an On-Chip Incoherent Multiprocessor Memory Hierarchy".
- Nima Honarmand, 2014. First Job: Assistant Professor, Department of Computer Science, Stony Brook University, Stony Brook, NY. Thesis: "Record and Deterministic Replay of Parallel Programs on Multiprocessors".
- Aditya Agrawal, 2014. First Job: Member of Research Staff, NVidia, Santa Clara, CA. Thesis: "Refresh Reduction in Dynamic Memories".
- Yuelu Duan, 2014. First Job: Member of Technical Staff, VMware, San Diego, CA. Thesis: "Techniques for Low Overhead Fences and Sequential Consistency Violation Recording".
- Xuehai Qian, 2013. Current Job: Assistant Professor, Department of Electrical Engineering, University of Southern California, Los Angeles, CA. Thesis: "Scalable and Flexible Bulk Architecture".
- Shanxiang Qi, 2013. First Job: Member of Technical Staff, Google, Mountain View, CA. Thesis: "Techniques to Detect and Avert Advanced Software Concurrency Bugs".
- Ulya Karpuzcu, 2012. First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN. Thesis: "Novel Many-Core Architectures for Energy-Efficiency".
- Abdullah Muzahid, 2012. Current Job: Assistant Professor, Department of Computer Science and Engineering, Texas A&M University, College Station, TX. Thesis: "Effective Architectural Support For Detecting Concurrency Bugs".
- Daniel Wonsun Ahn, 2012. Current Job: Assistant Professor, Department of Computer Science, University of Pittsburgh, Pittsburgh, PA. Thesis: "Software and Architecture Support for the BULK Multicore".
- Pablo Montesinos, 2009. First Job: Member of Research Staff, Samsung Laboratories, San Jose, CA. Thesis: "Practical Time Travel of Multiprocessor Systems".
- Brian Greskamp, 2009. First Job: Member of Research Staff, D. E. Shaw Research, New York, NY. Thesis: "Improving Per-Thread Performance on CMPs through Timing Speculation."
- Radu Teodorescu, 2008. First Job: Assistant Professor, Department of Computer Science and Engineering, Ohio State University, Columbus, OH. Thesis: "Multilayer Techniques to Address Parameter Variation".
- Abhishek Tiwari, 2008. First Job: Member of Technical Staff, Goldman Sachs, New York, NY. Thesis: "Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors".
- Luis Ceze, 2007. First Job: Assistant Professor, Department of Computer Science and Engineering, University of Washington, Seattle, WA. Thesis: "Bulk Operation and Data Coloring for Multiprocessor Programmability".
- James Tuck, 2007. First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC. Thesis: "Efficient Support for Speculative Tasking".
- Karin Strauss, 2007. First Job: Member of Research Staff, AMD Laboratories, Seattle, WA. Thesis: "Cache Coherence in Embedded-Ring Multiprocessors".
- Smruti R. Sarangi, 2007. Current Job: Assistant Professor, Department of Computer Science and Engineering, Indian Institute of Technology, New Delhi, India. Thesis: "Techniques to Mitigate the Effects of Congenital Faults in Processors".
- Jun Nakano, 2006. First Job: Member of Research Staff, IBM Research, Tokyo, Japan. Thesis: "Techniques to Address Unreliability and Variability of Computing Systems".
- Jose Renau, 2004. First Job: Assistant Professor, Department of Computer Engineering, University of California, Santa Cruz. Thesis: "Chip Multiprocessors with Speculative Multithreading: Design for Performance and Energy Efficiency".
- Milos Prvulovic, 2003. First Job: Assistant Professor, College of Computing, Georgia Institute of Technology, Atlanta, GA. Thesis: "Architectural Support for Reliable Parallel Computing".
- Jose Martinez, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY. Thesis: "Speculative Shared-Memory Architectures".
- Yan Solihin, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC. Thesis: "Improving Memory Performance Using Intelligent Memory."
- Michael Huang, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY. Thesis: "Managing Processor Adaptation for Energy Reduction and Temperature Control".
- Anthony Nguyen, 2002. Current Job: Member of Research Staff, Intel Corporation, Santa Clara, CA. Thesis: "High-Throughput Coherence Controllers".
- Marcelo Cintra, 2001. First Job: Lecturer, School of Informatics, University of Edinburgh, UK. Thesis: "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors".
- Seung-Moon Yoo, 2001. First Job: Member of Research Staff, IBM Research, Austin, TX. Thesis: "Design of Energy-Efficient SOCs with Deep Sub-Micron Circuit Techniques".
- Qiang Cao, 2000. First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA. Thesis: "Performance Characterization and Buffer Memory Optimization of Databases".
- Sujoy Basu, 2000. First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA. Thesis: "Design of Efficient Simple COMA Architectures".
- Yi Kang, 1999. First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA. Thesis: "An Intelligent Memory for Data Intensive Applications".
- Ye Zhang, 1999. First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA. Thesis: "Speculative Parallelization in DSM Multiprocessors".
- Pedro Trancoso, 1998. Current Job: Lecturer, Department of Computer Science, University of Cyprus, Cyprus. Thesis: "Optimizing Memory-Resident DSS Workloads for Caches".
- Venkata Krishnan, 1998. First Job: Microprocessor Design Group, DEC Shrewsbury, MA. Thesis: "Speculative Multithreading Architectures".
- Liuxi Yang, 1997. First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA. Thesis: "Using Advanced Memory Technologies to Build DSM Multiprocessors."
- David Koufaty, 1997. First Job: Member of Technical Staff, Intel Corp, Hillsboro, OR. Thesis: "Compiler Support to Hide Coherence Misses in Shared-Memory Multiprocessors".
- Zheng Zhang, 1996. First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA. Thesis: "Design Alternatives to Reduce Remote Conflict Misses in Shared-Memory Multiprocessors".
- Chun Xia, 1996. First Job: Member of Technical Staff, Sun Microsystems, Menlo Park, CA. Thesis: "Exploiting Multiprocessor Memory Hierarchies for Operating Systems."
Publications
- Conference Proceedings, Journals, and Books
- CXLfork: Fast Remote Fork over CXL Fabrics,
by Chloe Alverti, Stratos Psomadakis, Burak Ocalan, Shashwat Jaiswal, Tianyin Xu, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2025. [Presentation slides] - TAPAS: Thermal- and Power-Aware Scheduling for LLM Inference in the Cloud,
by Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Esha Choukse, Haoran Qiu, Rodrigo Fonseca, Josep Torrellas, Ricardo Bianchini,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2025. [Presentation slides] - Concord: Rethinking Distributed Coherence for Software Caches in Serverless Environments,
by Jovan Stojkovic, Chloe Alverti, Alan Andrade, Nikoleta Iliakopoulou, Hubertus Franke, Tianyin Xu, Josep Torrellas,
International Symposium on High-Performance Computer Architecture (HPCA), March 2025. [Presentation slides] - DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency,
by Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Josep Torrellas, Esha Choukse,
International Symposium on High-Performance Computer Architecture (HPCA), March 2025. [Presentation slides] - Mosaic: Harnessing the Micro-architectural Resources of Servers in Serverless Environments,
by Jovan Stojkovic, Esha Choukse, Enrique Saurez, Iñigo Goiri, Josep Torrellas,
International Symposium on Microarchitecture (MICRO), November 2024. [Presentation slides] - FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks,
by Hyoungwook Nam, Raghavendra Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2024. [Presentation slides] - Distributed-memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication,
by Isuru Ranawaka, Md Taufique Hussain, Charles Block, Gerasimos Gerogiannis, Josep Torrellas, Ariful Azad,
International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2024. [Presentation slides] - ACE Center: Energy-efficient Distributed Computing for the Next Decade and Beyond,
by Josep Torrellas,
ACM SIGARCH blog, June 2024. - HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs,
by Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2024. [Presentation slides] - EcoFaaS: Rethinking the Design of Serverless Environments for Energy Efficiency,
by Jovan Stojkovic, Nikoleta Iliakopoulou, Tianyin Xu, Hubertus Franke, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2024. [Presentation slides] - Practical Online Reinforcement Learning for Microprocessors with Micro-Armed Bandit,
by Gerasimos Gerogiannis and Josep Torrellas,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, July-August 2024. - Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM,
by Charles Block, Gerasimos Gerogiannis, Charith Mendis, Ariful Azad, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024. [Presentation slides] - Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud,
by Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024. Extended Version in arXiv:2405.12469v1. [Presentation slides] - Everywhere All at Once: Co-Location Attacks
on Public Cloud FaaS,
by Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2024. [Presentation slides] - MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs,
by Antonis Psistakis, Fabien Chaix, Josep Torrellas,
International Symposium on High-Performance Computer Architecture (HPCA), March 2024. [Presentation slides] - HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures,
by Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur,
International Symposium on High-Performance Computer Architecture (HPCA), March 2024. [Presentation slides] - Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making,
by Gerasimos Gerogiannis and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2023. [Presentation slides] - ACE Center for Evolvable Computing,
by Josep Torrellas,
The Project Repository Journal (PRj), Volume 17, June 2023. - RETROSPECTIVE: Bulk Disambiguation of Speculative Threads in Multiprocessors,
by Luis Ceze, James M. Tuck, Calin Cascaval, Josep Torrellas,
Collection of Retrospectives on Selected Papers from the Second 25 Years of the International Symposium on Computer Architecture (ISCA), June 2023. - μManycore: A Cloud-Native CPU for Tail at Scale,
by Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2023. [Presentation slides] - MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency,
by Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2023. [Presentation slides] - SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM,
by Gerasimos Gerogiannis, Serif Yesil, Damitha Lenadora, Dingyuan Cao, Charith Mendis, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2023. [Presentation slides] - Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes,
by Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2023. [Presentation slides] - WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning,
by Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas,
Symposium on Principles and Practice of Parallel Programming (PPoPP), February 2023. [Presentation slides] - Memory-Efficient Hashed Page Tables,
Jovan Stojkovic, Namrata Mantri, Dimitrios Skarlatos, Tianyin Xu, Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2023. [Presentation slides]. - SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution,
Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2023. [Presentation slides]. - Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker,
by Zirui Neil Zhao, Adam Morrison, Christopher Fletcher, Josep Torrellas,
USENIX Security Symposium, August 2022. [Presentation slides]. - Graphite: Optimizing Graph Neural Networks on CPUs Through Cooperative Software-Hardware Techniques,
Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2022. [Presentation slides]. - Cloak: Tolerating Non-Volatile Cache Read Latency,
Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos,
International Conference on Supercomputing (ICS), June 2022. [Presentation slides]. - Dense Dynamic Blocks: Optimizing SpMM for Processors with Vector and Matrix Units Using Machine Learning Techniques,
Serif Yesil, Jose E. Moreira, Josep Torrellas,
International Conference on Supercomputing (ICS), June 2022. [Presentation slides]. - Maya: Using Formal Control to Obfuscate Power Side Channels,
Raghavendra Pothukuchi, Sweta Pothukuchi, Petros Voulgaris, Alex Schwing, Josep Torrellas,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, May-June 2022. - Distributed Data Persistency,
Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, May-June 2022. - Parallel Virtualized Memory Translation with Nested Elastic Cuckoo Page Tables,
J. Stojkovic, D. Skarlatos, A. Kokolis, T. Xu, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2022. [Presentation slides]. - Pinned Loads: Taming Speculative Loads in Secure Processors,
Z. Zhao, H. Ji, A. Morrison, D. Marinov, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2022. [Presentation slides]. - Distributed Data Persistency,
Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2021. [Presentation slides]. Selected as Top Picks from Computer Architecture Conferences. - Maya: Using Formal Control to Obfuscate Power Side Channels,
Raghavendra Pothukuchi, Sweta Pothukuchi, Petros Voulgaris, Alex Schwing, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2021. [Presentation slides].
Details on the design of the formal controller are in Designing a Robust Controller for Obfuscating a Computer’s Power, Technical Report, June 2021. Selected as Top Picks from Computer Architecture Conferences. - Execution Dependence Extension (EDE): ISA Support for Eliminating Fences,
Thomas Shull, Nikos Nikoleris, Ilias Vougioukas, Wendy Elsasser, Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2021. [Presentation slides]. - BabelFish: Fusing Address Translations for Containers
by Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, May-June 2021. - Speculative Taint Tracking (STT): A Comprehensive
Protection for Speculatively Accessed Data
by Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher Fletcher,
Research Highlight, Communications of the ACM (CACM), 2021. - UniHeap: Managing Persistent Objects Across Managed Runtimes for Non-Volatile Memory,
Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang,
International Systems and Storage Conference (SYSTOR), June 2021. [Presentation slides]. - Jamais Vu: Thwarting Microarchitectural Replay Attacks,
Dimitrios Skarlatos, Zirui Neil Zhao, Riccardo Paccagnella, Christopher Fletcher, Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2021. [Presentation slides]. - Speculative Interference Attacks: Breaking Invisible Speculation Schemes,
M. Behnia, P. Sahu, R. Paccagnella, J. Yu, Z. Zhao, X. Zou, T. Unterluggauer, J. Torrellas, C. Rozas, A. Morrison, F. Mckeen, F. Liu, R. Gabor, C. Fletcher, A. Basak, A. Alameldeen,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2021. [Presentation slides]. - WiDir: A Wireless-Enabled Directory Cache Coherence Protocol,
Antonio Franques, Apostolos Kokolis, Sergi Abadal, Vimuth Fernando, Sasa Misailovic, Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2021. [Presentation slides]. - One Protocol to Rule Them All: Deep Reinforcement Learning Aided MAC for Wireless Network-on-Chips,
Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Sergi Abadal, Josep Torrellas, Haitham Hassanieh,
USENIX Symposium on Networked Systems Design and Implementation (NSDI), April 2021. [Presentation slides]. - Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores,
Antonio Franques, Sergi Abadal, Haitham Hassanieh, Josep Torrellas,
Design, Automation and Test in Europe Conference (DATE), February 2021. [Presentation slides]. - Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis
Zirui Neil Zhao, Houxiang Ji, Mengjia Yan, Jiyong Yu, Christopher W. Fletcher, Adam Morrison, Darko Marinov, and Josep Torrellas,
The International Symposium on Microarchitecture (MICRO), October 2020. [Presentation slides]. - P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks
Apostolos Kokolis, Thomas Shull, Jian Huang, and Josep Torrellas,
The International Symposium on Microarchitecture (MICRO), October 2020. [Presentation slides]. - SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs
Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara Baghsorkhi, and Josep Torrellas,
The International Symposium on Microarchitecture (MICRO), October 2020. [Presentation slides]. - Draco: Architectural and Operating System Support for System Call Security
Dimitrios Skarlatos, Qingrong Chen, Jianyan Chen, Tianyin Xu, and Josep Torrellas,
The International Symposium on Microarchitecture (MICRO), October 2020. [Presentation slides]. - Speeding Up SpMV for Power-Law Graph Analytics by Enhancing Locality and Vectorization
Serif Yesil, Azin Heidarshenas, Adam Morrison, and Josep Torrellas,
The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2020. [Presentation slides]. - SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors
Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, and Josep Torrellas,
The International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2020. [Presentation slides]. - BabelFish: Fusing Address Translations for Containers
by Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2020. [Presentation slides]. Selected as Top Picks from Computer Architecture Conferences. - Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution
by Jiyong Yu, Namrata Mantri, Josep Torrellas, Adam Morrison, and Christopher W. Fletcher,
International Symposium on Computer Architecture (ISCA), June 2020. [Presentation slides]. Selected as First Prize in Intel Hardware Security Academic Award. - SNUG: Architectural Support for Relaxed Concurrent Priority Queueing in Chip Multiprocessors
by Azin Heidarshenas, Tanmay Gangwani, Serif Yesil, Adam Morrison, and Josep Torrellas,
International Conference on Supercomputing (ICS), June 2020. [Presentation slides]. - V-Combiner: Speeding-up Iterative Graph Processing on a Shared-Memory Platform with Vertex Merging
by Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos, Sasa Misailovic, Adam Morrison and Josep Torrellas,
International Conference on Supercomputing (ICS), June 2020. [Presentation slides]. - Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism
by Dimitrios Skarlatos, Apostolos Kokolis, Tianyin Xu, and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2020. [Presentation slides]. [Video]. ASPLOS 2020 Best Paper Award. Also Selected as an Honorable Mention in IEEE Micro Top Picks from Computer Architecture Conferences.
- MicroScope: Enabling Microarchitectural Replay Attacks
by Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, and Christopher Fletcher,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, May-June 2020. - Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
by Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher Fletcher,
IEEE Micro Magazine, Top Picks in Computer Architecture Issue, May-June 2020. - Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication
by Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcon, and Albert Cabellos-Aparicio,
IEEE Transactions on Communications, vol. 68, no. 5, 2020. - Control Systems for Computing Systems: Making Computers Efficient with Modular, Coordinated and Robust Control
by Raghavendra Pothukuchi, Sweta Pothukuchi, Petros Voulgaris, and Josep Torrellas,
IEEE Control Systems Magazine, April, 2020. [Cover Article]. - Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures
by Mengjia Yan, Christopher W. Fletcher, and Josep Torrellas,
USENIX Security Symposium (USS), August 2020. [Presentation slides]. - Tangram: Integrated Control of Heterogeneous Computers
by Raghavendra Pradyumna Pothukuchi, Joseph L. Greathouse, Karthik Rao, Christopher Erb, Leonardo Piga, Petros Voulgaris, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2019. [Presentation slides]. - Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
by Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher Fletcher,
International Symposium on Microarchitecture (MICRO), October 2019. [Presentation slides]. MICRO 2019 Best Paper Award. Also Selected as a Top Picks from Computer Architecture Conferences. Also Research Highlight, Communications of the ACM (CACM). - Understanding Priority-Based Scheduling of Graph Algorithms on a Shared-Memory Platform
by Serif Yesil, Azin Heidarshenas, Adam Morrison, and Josep Torrellas,
International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2019. [Presentation slides]. - Designing Vertical Processors in Monolithic 3D
by Bhargava Gopireddy and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2019. [Presentation slides]. Selected as an Honorable Mention in IEEE Micro 2020 Top Picks from Computer Architecture Conferences. - SecDir: A Secure Directory to Defeat Directory Side-Channel Attacks
by Mengjia Yan, Jen-Yang Wen, Christopher Fletcher, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2019. [Presentation slides]. - MicroScope: Enabling Microarchitectural Replay Attacks
by Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, and Christopher Fletcher,
International Symposium on Computer Architecture (ISCA), June 2019. [Presentation slides]. Selected as a IEEE Micro 2020 Top Picks from Computer Architecture Conferences. - AutoPersist: An Easy-To-Use Java NVM Framework Based on Reachability
by Thomas Shull, Jian Huang, Josep Torrellas,
International Conference on Programming Language Design and Implementation (PLDI), June 2019. [Presentation slides]. - Reusable Inline Caching for JavaScript Performance
by Jiho Choi, Thomas Shull, and Josep Torrellas,
International Conference on Programming Language Design and Implementation (PLDI), June 2019. [Presentation slides]. - Replica: A Wireless Manycore for Communication-Intensive and Approximate Data
by Vimuth Fernando, Antonio Franques, Sergi Abadal, Sasa Misailovic, and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2019. [Presentation slides]. - Opportunistic Beamforming in Wireless Network-on-Chip
by Sergi Abadal, Adrian Marruedo, Antonio Franques, Hamidreza Taghvaee, Albert Cabellos-Aparicio, Jin Zhou, Josep Torrellas, and Eduard Alarcon,
International Symposium on Circuits and Systems (ISCAS), May 2019. [Presentation slides]. - QuickCheck: Using Speculation to Reduce the Overhead of Checks in NVM Frameworks
by Thomas Shull, Jian Huang, and Josep Torrellas,
International Conference on Virtual Execution Environments (VEE), April 2019. [Presentation slides]. - Designing a User-Friendly Java NVM Framework
by Thomas Shull, Jian Huang, and Josep Torrellas,
10th Non-Volatile Memories Workshop, March 2019. [Presentation slides]. - NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory
by Thomas Shull, Jiho Choi, Maria J. Garzaran, and Josep Torrellas,
International Symposium on High-Performance Computer Architecture (HPCA), February 2019. [Presentation slides]. - PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems
by Apostolos Kokolis, Dimitrios Skarlatos, and Josep Torrellas,
International Symposium on High-Performance Computer Architecture (HPCA), February 2019. [Presentation slides]. - Inter-Disciplinary Research Challenges in Computer Systems for the 2020s
by Albert Cohen, Xipeng Shen, Josep Torrellas, James Tuck, and Yuanyuan Zhou,
Report on the NSF-sponsored Visioning Workshop on Inter-Disciplinary Research Challenges in Computer Systems, March 2018. The ACM Digital Library also has a copy of the report. - Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World
by Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher Fletcher, Roy Campbell, and Josep Torrellas,
IEEE Symposium on Security and Privacy (SP), May 2019. [Presentation slides]. Also, Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2018, [slides from the talk]. - InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
by Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2018.
Corrected version of the paper.
One-page explanation of the correction.
[Presentation slides]. Honorable Mention in 2019 IEEE Micro's Top Picks from Computer Architecture Conferences. -
Structured Singular Value Control for Modular Resource Management in Multilayer Computers
by Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Josep Torrellas, and Petros Voulgaris,
IEEE Conference on Decision and Control (CDC), December 2018. [Presentation slides]. - Biased
Reference Counting: Limiting Atomic Operations in Reference Counting for Garbage Collection
by Jiho Choi, Thomas Shull, and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), November 2018. [Presentation slides]. - An Empirical Study of the Effect of Source-level Loop
Transformations on Compiler Stability
by Zhangxiaowen Gong, Zhi Chen, Justin Szaday, David Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David Padua, Alexander Veidenbaum, Alexandru Nicolau, and Josep Torrellas,
Conference on Object-Oriented Programming, Systems, Languages and Applications (OOPSLA), November 2018. [Presentation slides]. - Defining a High-Level Programming Model for Emerging NVRAM Technologies
by Thomas Shull, Jian Huang, and Josep Torrellas,
International Conference on Managed Languages and Runtimes (ManLang), September 2018. [Presentation slides]. - HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs
by Bhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2018. [Presentation slides]. - Yukta: Multilayer Resource Controllers to Maximize Efficiency
by Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros Voulgaris, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2018. [Presentation slides]. - Millimeter-Wave Propagation Within a
Computer Chip Package
by Xavier Timoneda, Sergi Abadal, Albert Cabellos-Aparicio, Dionysios Manessis, Jin Zhou, Antonio Franques, Josep Torrellas and Eduard Alarcon,
International Symposium on Circuits and Systems (ISCAS), May 2018. [Presentation slides]. - RnR-Safe: Record-Replay Architecture as a General Security Framework
by Yasser Shalabi, Mengjia Yan, Nima Honarmand, Ruby Lee, and Josep Torrellas,
International Symposium on High-Performance Computer Architecture (HPCA), February 2018. [Presentation slides]. - OrthoNoC: A Broadcast-Oriented
Dual-Plane Wireless Network-on-Chip Architecture
by Sergi Abadal, Josep Torrellas, Eduard Alarcon, and Albert Cabellos-Aparicio,
IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume: 29 Issue: 3, March 2018. - Medium Access Control in Wireless Network-on-Chip:
A Context Analysis
by Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcon, and Albert Cabellos-Aparicio,
IEEE Communications Magazine, January 2018. - PageForge: A Near-Memory Content-Aware Page-Merging Architecture
by Dimitrios Skarlatos, Nam Sung Kim, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2017. [Presentation slides]. - Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks
by Aditya Agrawal, Josep Torrellas, and Sachin Idgunji,
International Symposium on Microarchitecture (MICRO), October 2017. [Presentation slides]. - LORE: A Loop Repository for the Evaluation of Compilers
by Zhi Chen, Zhangxiaowen Gong, Justin Szaday, David Wong, David Padua, Alexandru Nicolau, Alexander Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, and Gerald DeJong,
International Symposium on Workload Characterization (IISWC), October 2017. [Presentation slides]. - Sthira: A Formal Approach to Minimize
Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency
by Raghavendra Pothukuchi, Amin Ansari, Bhargava Gopireddy, and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2017. Best Paper Nominee. [Presentation slides]. - ShortCut: Architectural Support for Fast
Object Access in Scripting Languages
by Jiho Choi, Thomas Shull, Maria Garzaran, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2017. [Presentation slides]. - Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks
by Mengjia Yan, Bhargava Gopireddy, Thomas Shull, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2017. [Presentation slides]. -
Survive: Pointer-based In-DRAM Incremental Checkpointing
for Low-Cost Data Persistence and Rollback-Recovery
by Amirhossein Mirhosseini, Aditya Agrawal, and Josep Torrellas,
IEEE Computer Architecture Letters (CAL), July-December 2017. -
Compiler Support for Software Cache Coherence
by Sanket Tavarageri, Wooil Kim, Josep Torrellas, and P. Sadayappan,
International Conference on High Performance Computing, Data, and Analytics (HiPC), December 2016. [Presentation slides] -
ReplayConfusion: Detecting Cache-based Covert Channel Attacks Using Record and Replay
by Mengjia Yan, Yasser Shalabi, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2016. [Presentation slides] -
Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks
by Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert Pilawa, Ulya Karpuzcu, Radu Teodorescu, Nam Sung Kim, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), October 2016. [Presentation slides] -
A MAC Protocol for Reliable Broadcast Communications in Wireless Network-on-Chip
by Albert Mestres, Sergi Abadal, Josep Torrellas, Eduard Alarcon, and Albert Cabellos-Aparicio,
International Workshop on Network on Chip Architectures (NoCArc), October 2016. [Presentation slides] -
WearCore: A Core for Wearable Workloads
by Sanyam Mehta and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2016. [Presentation slides] -
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures
by Raghavendra Pothukuchi, Amin Ansari, Petros Voulgaris, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2016. [Presentation slides]
Details on the model and methodology are in A Guide to Design MIMO Controllers for Architectures, Technical Report, April 2016. -
Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy
by Wooil Kim, Sanket Tavarageri, Ponnuswamy Sadayappan, and Josep Torrellas,
International Parallel and Distributed Processing Symposium (IPDPS), May 2016. [Presentation slides] -
CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization
by Tanmay Gangwani, Adam Morrison, and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2016. [Presentation slides] -
WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication
by Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcon, and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2016. [Presentation slides] -
SCsafe: Logging Sequential Consistency Violations Continuously and Precisely
by Yuelu Duan, David Koufaty, and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), March 2016. [Presentation slides] -
ScalCore: Designing a Core for Voltage Scalability
by Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, and Asit Mishra,
International Symposium on High Performance Computer Architecture (HPCA), March 2016. [Presentation slides] -
Asymmetric Memory Fences: Optimizing Both Performance and
Implementability
by Yuelu Duan, Nima Honarmand and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2015. [Presentation slides] -
Extreme-Scale Computer Architecture
by Josep Torrellas,
National Science Review, Special Issue on High Performance Computing, Oxford University Press, 2015. -
Many-Core Architecture for NTC: Energy Efficiency from the Ground Up
by Josep Torrellas,
Near Threshold Computing - Technology, Methods and Applications, Michael Huebner and Cristina Silvano Editors, Springer, 2015. -
Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy
by Ehsan Totoni, Josep Torrellas, and Laxmikant V. Kale,
International Conference for High Performance Computing, Networking, Storage and Analysis (SC), November 2014. [Presentation slides] -
Replay Debugging: Leveraging Record and Replay for Program Debugging
by Nima Honarmand and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2014. [Presentation slides] -
OmniOrder: Directory-Based Conflict Serialization of Transactions
by Xuehai Qian, Benjamin Sahelices, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2014. [Presentation slides] -
Improving JavaScript Performance by Deconstructing the Type System
by Wonsun Ahn, Jiho Choi, Thomas Shull, Maria Garzaran, and Josep Torrellas,
International Conference on Programming Language Design and Implementation (PLDI), June 2014. Distinguished Paper Award. [Presentation slides] -
Making Parallel Programming Easy: Research Contributions from Illinois
by Josep Torrellas, Sarita V. Adve, Vikram S. Adve, Danny Dig, Minh N. Do, Maria Jesus Garzaran, John C. Hart, Thomas S. Huang, Wen-mei W. Hwu, Samuel T. King, Darko Marinov, Klara Nahrstedt, David A. Padua, Madhusudan Parthasarathy, Sanjay J. Patel, and Marc Snir,
September 2013. -
RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors
by Nima Honarmand and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014. [Presentation slides] -
Extreme-Scale Computer Architecture: Energy Efficiency from the Ground Up
by Josep Torrellas,
Design Automation and Test in Europe (DATE), March 2014. [Presentation slides] -
Mosaic: Exploiting the Spatial Locality of Process Variation to
Reduce Refresh Energy in On-Chip eDRAM Modules
by Aditya Agrawal, Amin Ansari, and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2014. [Presentation slides] -
Tangle: Route-Oriented Dynamic Voltage Minimization for
Variation-Afflicted, Energy-Efficient On-Chip Networks
by Amin Ansari, Asit Mishra, Jianping Xu, and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2014. Best Paper Nominee in HPCA. Honorable Mention in 2015 IEEE Micro's Top Picks from Computer Architecture Conferences. [Presentation slides] -
Dynamically Detecting and Tolerating IF-Condition Data Races
by Shanxiang Qi, Abdullah Muzahid, Wonsun Ahn, and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2014. [Presentation slides] -
BulkCommit: Scalable and Fast Commit of Atomic Blocks in a Lazy
Multiprocessor Environment
by Xuehai Qian, Benjamin Sahelices, Josep Torrellas, and Depei Qian,
International Symposium on Microarchitecture (MICRO), December 2013. [Presentation slides] -
Coping with Parametric Variation at Near-Threshold Voltages
by Ulya Karpuzcu, Nam Sung Kim, and Josep Torrellas,
IEEE Micro Magazine, Special Issue on Reliability-Aware Microarchitecture Design, Volume:33 Issue:4, July-Aug. 2013. -
QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs
by Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, and Justin Gottschlich (Intel), and Nima Honarmand, Nathan Dautenhahn, Sam King and Josep Torrellas (UIUC),
International Symposium on Computer Architecture (ISCA), June 2013. [Presentation slides] -
WeeFence: Toward Making Fences Free in TSO
by Yuelu Duan, Abdullah Muzahid, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2013. [Presentation slides] -
DeAliaser: Alias Speculation Using Atomic Region Support
by Wonsun Ahn, Yuelu Duan and Josep Torrellas,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2013. [Presentation slides] -
Cyrus: Unintrusive Application-Level Record-Replay for Replay Parallelism
by Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel King, Gilles Pokam and Cristiano Pereira,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2013. [Presentation slides] -
Volition: Scalable and Precise Sequential Consistency Violation Detection
by Xuehai Qian, Benjamin Sahelices, Josep Torrellas and Depei Qian,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2013. [Presentation slides] -
Runnemede: An Architecture for Ubiquitous High-Performance Computing
by Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua Fryman, Ivan Ganev, Roger A. Golliver, Rob Knauerhase, Richard Lethin, Benoit Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, and Jianping Xu,
International Symposium on High Performance Computer Architecture (HPCA), February 2013. [Presentation slides] -
EnergySmart: Toward Energy-Efficient Manycores for Near-Threshold Computing
by Ulya R. Karpuzcu, Abhishek Sinkar, Nam Sung Kim, and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2013. [Presentation slides] -
Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache
Hierarchies
by Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas,
International Symposium on High Performance Computer Architecture (HPCA), February 2013. [Presentation slides] -
Illusionist: Transforming Lightweight Cores into Aggressive Cores on
Demand
by Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, and Scott Mahlke,
International Symposium on High Performance Computer Architecture (HPCA), February 2013. [Presentation slides] -
Vulcan: Hardware Support for Detecting
Sequential Consistency Violations Dynamically
by Abdullah Muzahid, Shanxiang Qi and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2012. [Video of a presentation at UIUC]. [Presentation slides] -
FlexRAM: Toward an Advanced Intelligent Memory System.
A Retrospective Paper
by Josep Torrellas,
International Conference on Computer Design (ICCD), September 2012. [Presentation slides] -
21st Century Computer Architecture
by Mark Hill, Sarita Adve, Luis Ceze, Mary-Jane Irwin, David Kaeli, Margaret Martonosi, Josep Torrellas, Thomas Wenisch, David Wood and Katherine Yelick,
A Community White Paper, Computing Community Consortium, May 2012. [Presentation slides] -
VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity
of Manycores to Process Variations at Near-Threshold Voltages
by Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim and Josep Torrellas,
International Conference on Dependable Systems and Networks (DSN), June 2012. [Presentation slides] -
Comparing the Power and Performance of Intel's SCC to State-of-the-Art CPUs and GPUs
by Ehsan Totoni, Babak Behzad, Swapnil Ghike and Josep Torrellas,
International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2012. [Presentation slides] -
BulkSMT: Designing SMT Processors for Atomic-Block Execution
by Xuehai Qian, Benjamin Sahelices and Josep Torrellas,
International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides] -
Pacman: Tolerating Asymmetric Data Races with Unintrusive Hardware
by Shanxiang Qi, Norimasa Otsuki, Lois Orosa, Abdullah Muzahid, and Josep Torrellas,
International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides] -
BulkCompactor: Optimized Deterministic Execution via Conflict-Aware
Commit of Atomic Blocks
by Yuelu Duan, Xing Zhou, Wonsun Ahn, and Josep Torrellas,
International Symposium on High Perfomance Computer Architecture (HPCA), February 2012. [Presentation slides] -
FlexBulk: Intelligently Forming Atomic Blocks in
Blocked-Execution Multiprocessors to Minimize Squashes
by Rishi Agarwal and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2011. [Presentation slides] -
Rebound: Scalable Checkpointing for Coherent Shared Memory
by Rishi Agarwal, Pranav Garg, and Josep Torrellas,
International Symposium on Computer Architecture (ISCA), June 2011. [Presentation slides] -
Thread-Level Speculation
by Josep Torrellas,
Encyclopedia of Parallel Computing, Springer Science+Business Media LLC, May 2011. -
Cache-Only Memory Architecture
by Josep Torrellas,
Encyclopedia of Parallel Computing, Springer Science+Business Media LLC, May 2011. -
Failure is not an Option: Popular Parallel Programming
by J.Torrellas, M.Oskin, S.Adve, G.Almasi, L.Ceze, A.Chtchelkanova, C.Das, B.Feiereisen, W.Harrod, M.Hill, J.Hiller, S.Kannan, K.Kant, C.Kozyrakis, J.Larus, R.Murphy, O.Mutlu, S.Narayanasamy, K.Olukotun, Y.Patt, A.Sivasubramaniam, K.Skadron, K.Strauss, S.Swanson, and D.Tullsen,
Report from the CCC-Sponsored First Workshop on Advancing Computer Architecture Research (ACAR-1),
released October 2010. [Summary slides] -
Laying a New Foundation for IT: Computer Architecture for 2025 and Beyond
by M.Oskin, J.Torrellas, C.Das, J.Davis, S.Dwarkadas, L.Eeckhout, B.Feiereisen, D.Jimenez, M.Hill, M.Kim, J.Larus, M.Martonosi, O.Mutlu, K.Olukotun, A.Putnam, T.Sherwood, J.Smith, D.Wood, and C.Zilles,
Report from the CCC-Sponsored Second Workshop on Advancing Computer Architecture Research (ACAR-2),
released December 2010. [Summary slides] -
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
by Xuehai Qian, Wonsun Ahn, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2010. (17% acceptance rate) [Presentation slides] -
AtomTracker: A Comprehensive Approach to Atomic Region Inference and
Violation Detection
by Abdullah Muzahid, Norimasa Otsuki, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2010. (17% acceptance rate) [Presentation slides] -
InstantCheck: Checking the Determinism of Parallel Programs Using
On-the-fly Incremental Hashing
by Adrian Nistor, Darko Marinov, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2010. (17% acceptance rate) [Presentation slides] -
LeadOut: Composing Low-Overhead Frequency-Enhancing Techniques for Single-Thread
Performance in Configurable Multicores
by Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas,
16th International Symposium on High-Performance Computer Architecture (HPCA), January 2010. [Presentation slides] -
The Bulk Multicore Architecture for Improved Programmability
by Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, and Milos Prvulovic,
Communications of the ACM (CACM), December 2009. [Presentation slides] -
Architectures for Extreme-Scale Computing
by Josep Torrellas,
IEEE Computer, November 2009. [Presentation slides] -
BulkCompiler: High-Performance Sequential Consistency through Cooperative
Compiler and Hardware Support
by Wonsun Ahn, Shanxiang Qi, Jae-Woo Lee, Marios Nicolaides, Xing Fang, Josep Torrellas, David Wong, and Samuel Midkiff,
International Symposium on Microarchitecture (MICRO), December 2009. [Presentation slides] -
The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration
by Ulya R. Karpuzcu, Brian Greskamp and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2009. Best Paper Award. [Presentation slides] -
Light64: Lightweight Hardware Support for Data Race Detection during
Systematic Testing of Parallel Programs
by Adrian Nistor, Darko Marinov, and Josep Torrellas,
International Symposium on Microarchitecture (MICRO), December 2009. [Presentation slides] -
Hardware and Software Approaches for
Deterministic Multiprocessor Replay of Concurrent Programs
by Gilles Pokam, Cristiano Pereira, Klaus Danne, Lynda Yang, Samuel King, and Josep Torrellas,
Intel Technology Journal, Issue on Addressing the Challenges of Tera-Scale Computing, Vol. 13, Issue 4, December 2009. -
SigRace: Signature-Based Data Race Detection
by Abdullah Muzahid, Dario Suarez, Shanxiang Qi, and Josep Torrellas,
36th Annual International Symposium on Computer Architecture (ISCA), June 2009. [Presentation slides] -
Two Hardware-based Approaches for Deterministic Multiprocessor Replay
by Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas,
Research Highlight, Communications of the ACM (CACM), June 2009. -
Lessons Learned During the Development of the CapoOne
Deterministic Multiprocessor Replay System
by Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King, and Josep Torrellas,
Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), June 2009. [Presentation slides] -
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and
Optimization
by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2009. -
Capo: A Software-Hardware Interface for Practical Deterministic
Multiprocessor Replay
by Pablo Montesinos, Matthew Hicks, Samuel T. King, and Josep Torrellas,
14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009. [Presentation slides] -
BubbleWrap: Popping CMP Cores for Sequential Acceleration
by Brian Greskamp, R. Ulya Karpuzcu, and Josep Torrellas,
Wild and Crazy Ideas Session, at 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009. Best Idea Award. [Presentation slides] -
BlueShift: Designing Processors for Timing Speculation from the Ground Up
by Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, and Craig Zilles,
15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009. [Presentation slides] -
Programming and Debugging Shared Memory Programs with Data Coloring
by Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, and Josep Torrellas,
Workshop on Compilers for Parallel Computing (CPC), January 2009. - Techniques to Mitigate the Effects of Congenital Faults in Processors
by Smruti R. Sarangi and Josep Torrellas
160 pages, ISBN: 978-3-639-04637-3, VDM Verlag, 2008. -
Facelift: Hiding and Slowing Down Aging in Multicores
by Abhishek Tiwari and Josep Torrellas,
41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides] -
EVAL: Utilizing Processors with Variation-Induced Timing Errors
by Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas,
41st International Symposium on Microarchitecture (MICRO), November 2008. [Presentation slides] -
DeLorean: Recording and Deterministically Replaying
Shared-Memory Multiprocessor Execution Efficiently
by Pablo Montesinos, Luis Ceze, and Josep Torrellas,
35th Annual International Symposium on Computer Architecture (ISCA), June 2008. [Presentation slides] -
Variation-Aware Application Scheduling and Power Management for Chip
Multiprocessors
by Radu Teodorescu and Josep Torrellas,
35th Annual International Symposium on Computer Architecture (ISCA), June 2008. [Presentation slides] -
An Updated Evaluation of ReCycle
by Abhishek Tiwari and Josep Torrellas,
7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides] -
Using Register Lifetime Predictions to Protect Register Files
Against Soft Errors
by Pablo Montesinos, Wei Liu, and Josep Torrellas,
IEEE Transactions on Dependable and Secure Computing (IEEE TDSC), To Appear, 2008. -
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and
Optimization
by James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas,
13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008. [Presentation slides] -
Concurrency Control with Data Coloring
by Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, and Josep Torrellas,
Workshop on Memory Systems Performance and Correctness (MSPC), March 2008. -
OpenSPARC: An Open Platform for Hardware Reliability Experimentation
by Ishwar Parulkar, Alan Wood, James C. Hoe, Babak Falsafi, Sarita Adve, Josep Torrellas, and Subhasish Mitra,
Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2008. [Presentation slides] -
VARIUS: A Model of Process Variation and Resulting Timing Errors
for Microarchitects
by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008. [Presentation slides] -
Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
by Karin Strauss, Xiaowei Shen, and Josep Torrellas,
40th International Symposium on Microarchitecture (MICRO), December 2007. [Presentation slides] -
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
by Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas,
40th International Symposium on Microarchitecture (MICRO), December 2007. [Presentation slides] -
CAP: Criticality Analysis for Power-Efficient Speculative
Multithreading
by James Tuck, Wei Liu, and Josep Torrellas,
International Conference on Computer Design (ICCD), October 2007. [Presentation slides] -
Estimating Design Time for System Circuits
by Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau,
International Conference on Very Large Scale Integration (VLSI-SoC), October 2007. -
Paceline: Improving Single-Thread Performance
in Nanoscale CMPs through Core Overclocking
by Brian Greskamp and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007. [Presentation slides] -
BulkSC: Bulk Enforcement of Sequential Consistency
by Luis Ceze, James M. Tuck, Pablo Montesinos, and Josep Torrellas,
34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [Presentation slides] -
ReCycle: Pipeline Adaptation to Tolerate Process Variation
by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas,
34th Annual International Symposium on Computer Architecture (ISCA), June 2007. [Presentation slides]
An updated version with a more realistic pipeline model appears in An Updated Evaluation of ReCycle
by Abhishek Tiwari and Josep Torrellas,
7th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2008. [Presentation slides] -
VARIUS: A Model of Parameter Variation and Resulting Timing Errors
for Microarchitects
by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas,
Workshop on Architectural Support for Gigascale Integration (ASGI), June 2007. -
Using Register Lifetime Predictions to Protect Register Files
Against Soft Errors
by Pablo Montesinos, Wei Liu, and Josep Torrellas,
37th International Conference on Dependable Systems and Networks (DSN), June 2007. [Presentation slides]
This is an extension of Shield: Cost-Effective Soft-Error Protection for Register Files
Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006. [Presentation slides] -
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
by Brian Greskamp, Smruti Sarangi, and Josep Torrellas,
International Symposium on Circuits and Systems (ISCAS),
Special Session: Circuit Design in the Presence of Device Variability, May 2007. [Presentation slides] -
A Model for Timing Errors in Processors with Parameter Variation
by Smruti Sarangi, Brian Greskamp, and Josep Torrellas,
8th International Symposium on Quality Electronic Design (ISQED), March 2007. -
Patching Processor Design Errors with Programmable Hardware
by Smruti Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, and Josep Torrellas,
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2007. -
Colorama: Architectural Support for Data-Centric Synchronization
by Luis Ceze, Pablo Montesinos, Christoph von Praun, and Josep Torrellas,
13th International Symposium on High-Performance Computer Architecture (HPCA), February 2007. [Presentation slides] -
Phoenix: Detecting and Recovering from Permanent Processor
Design Bugs with Programmable Hardware
by Smruti R. Sarangi, Abhishek Tiwari, and Josep Torrellas,
39th International Symposium on Microarchitecture (MICRO), December 2006. Best Paper Award. [Presentation slides] -
Scalable Cache Miss Handling for High Memory-Level Parallelism
by James Tuck, Luis Ceze, and Josep Torrellas,
39th International Symposium on Microarchitecture (MICRO), December 2006. [Presentation slides] -
PathExpander: Architectural Support for Increasing the Path Coverage
of Dynamic Bug Detection
by Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, and Josep Torrellas,
39th International Symposium on Microarchitecture (MICRO), December 2006. -
Shield: Cost-Effective Soft-Error Protection for Register Files
by Pablo Montesinos, Wei Liu, and Josep Torrellas,
Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006. [Presentation slides] -
Accurate and Efficient Filtering for the Intel Thread Checker Race Detector
by Paul Sack, Brian E Bliss, Zhiqiang Ma, Paul Petersen, and Josep Torrellas,
Workshop on Architectural and System Support for Improving Software Dependability (ASID), October 2006. [Presentation slides] - Bulk Disambiguation of
Speculative Threads in Multiprocessors
by Luis Ceze, James M. Tuck, Calin Cascaval, and Josep Torrellas,
33rd Annual International Symposium on Computer Architecture (ISCA), June 2006. [Presentation slides] -
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops
in Embedded-Ring Multiprocessors
by Karin Strauss, Xiaowei Shen, and Josep Torrellas,
33rd Annual International Symposium on Computer Architecture (ISCA), June 2006. [Presentation slides] -
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
International Conference on Dependable Systems and Networks (DSN), June 2006. [Presentation slides] -
Designing Hardware that Supports Cycle-Accurate Deterministic Replay
by Brian Greskamp, Smruti R. Sarangi, and Josep Torrellas,
Workshop on Complexity-Effective Design (WCED), June 2006. -
Rapid Prototyping in Architecture Research Using
Hardware Hooks in COTS Systems
by Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas,
Workshop on Architectural Research Prototyping (WARP), June 2006. -
CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses
by Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas,
ACM Transactions on Architecture and Code Optimization (TACO), June 2006. -
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback
by Radu Teodorescu, Jun Nakano, and Josep Torrellas,
IEEE Micro Magazine, IEEE, Inc., vol. 26, September-October, 2006. - POSH: A TLS Compiler that Exploits Program Structure,
by Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas,
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006. [Presentation slides] -
ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers
by Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, and Josep Torrellas,
12th International Symposium on High-Performance Computer Architecture (HPCA), February 2006. [Presentation slides] - Energy-Efficient Thread-Level
Speculation on a CMP
by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
IEEE Micro Magazine, Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006. - Are We Ready for High Memory-Level Parallelism?,
by Luis Ceze, James Tuck, and Josep Torrellas,
Workshop on Memory Performance Issues (WMPI), February 2006. [Presentation slides] - Guest Editor's Introduction
by Josep Torrellas,
IEEE Micro Magazine, Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006. - ReSlice: Selective Re-Execution of Long-Retired Misspeculated
Instructions Using Forward Slicing
by Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou,
38th International Symposium on Microarchitecture (MICRO), November 2005. [Presentation slides] -
POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure
by Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas,
Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. [Presentation slides] -
A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads
by Mingliang Wei, Marc Snir, Josep Torrellas, and R. Brett Tremaine
Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005. [Presentation slides]
Additional details of the Processor can be found in:
A Brief Description of the NMP ISA and Benchmarks
by Mingliang Wei, Marc Snir, Josep Torrellas, and R. Brett Tremaine
Technical Report No. UIUCDCS-R-2005-2633, February 2005. -
Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in
Multiprocessors
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
ACM Transactions on Architecture and Code Optimization (TACO), Vol. 2, Num. 3, September 2005. - Thread-Level Speculation on a CMP Can Be Energy Efficient
by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas,
2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides] - Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors:
Microarchitecture and Compilation
Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas,
2005 ACM International Conference on Supercomputing (ICS), June 2005. [Presentation slides] -
The Design Complexity of Program Undo Support in a General-Purpose Processor
by Radu Teodorescu and Josep Torrellas,
Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA, June 2005. [Presentation slides] -
Empowering Software Debugging Through Architectural Support for Program Rollback
by Radu Teodorescu and Josep Torrellas,
Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005. [Presentation slides] -
Deploying Architectural Support for Software Defect Detection in Future Processors
by Yuanyuan Zhou and Josep Torrellas,
Workshop on the Evaluation of Software Defect Detection Tools (BUGS), in conjunction with PLDI, June 2005. -
Prototyping Architectural Support for Program Rollback Using FPGAs
by Radu Teodorescu and J. Torrellas,
2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005. [Presentation slides]
A one-page summary can be found as
Prototyping Architectural Support for Program Rollback: An Application to Software Debugging
Workshop on Architecture Research using FPGA Platforms, in conjunction with HPCA-11, February 2005. [Presentation slides] -
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
by Luis Ceze, Karin Strauss, James Tuck, Jose Renau and Josep Torrellas,
IEEE Computer Architecture Letters (CAL), IEEE, Inc., December 2004. -
Efficient and Flexible Architectural Support for Dynamic Monitoring
by Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, and Josep Torrellas,
ACM Transactions on Architecture and Code Optimization (TACO), December 2004. - iWatcher: Simple and General
Architectural Support for Software Debugging
by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2004. -
AccMon: Automatically Detecting Memory-Related Bugs
via Program Counter-Based Invariants
by Pin Zhou, Wei Liu, Fei Long, Shan Lu, Feng Qin, Yuanyuan Zhou, Sam Midkiff and Josep Torrellas,
37th International Symposium on Microarchitecture (MICRO), December 2004. -
iWatcher: Efficient Architectural Support for Software Debugging
by Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas,
31th Annual International Symposium on Computer Architecture (ISCA), June 2004. [Presentation slides] - Speculative Synchronization
by Jose Martinez and Josep Torrellas,
IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November-December 2003. - High Performance Memory Systems
by David Kaeli, Haldun Hadimioglu, Jeff Kuskin, Ashwini Nanda and Josep Torrellas, editors
290 pages, ISBN: 0-387-00310-X, Springer-Verlag, New York, 2003. - Managing Multiple Low-Power Adaptation Techniques: The Positional Approach
by Michael Huang, Jose Renau and Josep Torrellas,
Sidebar, Special Issue on Power-Aware Computing, IEEE Computer, December 2003. - Design Trade-offs in High-Throughput Coherence Controllers
by Anthony Nguyen and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003. [Presentation slides] - Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2003. [Presentation slides] - ReEnact: Using Thread-Level Speculation to Debug Data Races in Multithreaded Codes
by Milos Prvulovic and Josep Torrellas,
30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides] - Positional Adaptation of Processors: Application to Energy Reduction
by Michael Huang, Jose Renau, and Josep Torrellas,
30th Annual International Symposium on Computer Architecture (ISCA), June 2003. [Presentation slides] - Programming the FlexRAM Parallel Intelligent Memory System
by Basilio Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas,
International Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003. [Presentation slides] - Correlation Prefetching with a User-Level Memory Thread
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
IEEE Transactions on Parallel and Distributed Computing (TPDS), June 2003. - Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
9th International Symposium on High-Performance Computer Architecture (HPCA), February 2003. [Presentation slides] - Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
by José F. Martínez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas,
35th International Symposium on Microarchitecture (MICRO), November 2002. [Presentation slides] - Speculative Synchronization: Applying Thread-Level Speculation to Parallel Applications
by José F. Martínez and Josep Torrellas,
10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. [Presentation slides] - Software Trace Cache for Commercial Applications
by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero,
International Journal of Parallel Processing (IJPP), Vol. 30, Number 5, pp. 373-395, October 2002. - Energy-Efficient Hybrid Wakeup Logic
by Michael Huang, Jose Renau, and Josep Torrellas,
International Symposium on Low Power Electronics and Design (ISLPED), August 2002. [Presentation slides] - Using a User-Level Memory Thread for Correlation Prefetching
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
29th Annual International Symposium on Computer Architecture (ISCA), May 2002. [Presentation slides] - ReVive: Cost-Effective Architectural
Support for Rollback Recovery in Shared-Memory Multiprocessors
by Milos Prvulovic, Zheng Zhang, and Josep Torrellas
29th Annual International Symposium on Computer Architecture (ISCA), May 2002. [Presentation slides]
In the paper, there is a typo in the Y-Axes of Figs 9 and 10. The corrected plots are here. - Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
by Marcelo Cintra and Josep Torrellas,
Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002. [Presentation slides] - Compiler-Assisted Software and Hardware Support for Reduction Operations
by F. Dang, M. Garzaran, M. Prvulovic, Y. Zhang, A. Jula, H. Yu, N. Amato, L. Rauchwerger, and J. Torrellas,
NSF Workshop on Next Generation Systems, April 2002. - Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001. - Adaptively Mapping Code in an Intelligent Memory Architecture
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001. - Automatic Code Mapping on an Intelligent Memory Architecture
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001. - Prefetching in an Intelligent Memory Architecture Using a Helper Thread
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
Best Paper Award. Fifth Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC), December 2001. - Profile-Based Energy Reduction for High-Performance Processors
by Michael Huang, Jose Renau, and Josep Torrellas,
Fourth Workshop on Feedback Directed and Dynamic Optimization (FDDO), December 2001. - The Design of DEETM: A Framework for Dynamic Energy Efficiency and Temperature Management
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
Journal of Instruction-Level Parallelism (JILP), Vol. 3, October 2001. - Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors
by Maria Jesus Garzaran, Milos Prvulovic, Alin Jula, Hao Yu, Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas
International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2001. [Presentation slides] - L1 Data Cache Decomposition for Energy Efficiency
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
International Symposium on Low Power Electronics and Design (ISLPED), August 2001. - Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
by Milos Prvulovic, Maria Jesus Garzaran, Lawrence Rauchwerger, and Josep Torrellas,
28th Annual International Symposium on Computer Architecture (ISCA), June 2001. [Presentation slides] - Speculative Locks for Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors
by José F. Martínez and Josep Torrellas,
Workshop on Memory Performance Issues, June 2001. [Presentation slides]
Published as a chapter in High Performance Memory Systems, Springer-Verlag, New York, 2003. - Software Logging under Speculative Parallelization
by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
Workshop on Memory Performance Issues, June 2001. [Presentation slides]
Published as a chapter in High Performance Memory Systems, Springer-Verlag, New York, 2003. - Exploiting Intelligent Memory for Database Workloads
by Pedro Trancoso and Josep Torrellas,
Workshop on Memory Performance Issues, June 2001.
Published as a chapter in High Performance Memory Systems, Springer-Verlag, New York, 2003. - The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
by Venkata Krishnan and Josep Torrellas,
International Journal of Parallel Processing (IJPP), Vol. 29, Number 1, pp. 3-33, February 2001. - Automatically Mapping Code on an Intelligent Memory Architecture
by Jaejin Lee, Yan Solihin, and Josep Torrellas,
Seventh International Symposium on High-Performance Computer Architecture (HPCA), January 2001. [Presentation slides]
An extended version of it appears in
IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001. - A Framework for Dynamic Energy Efficiency and Temperature Management
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
33rd International Symposium on Microarchitecture (MICRO), December 2000. [Presentation slides]
The power model used is discussed in CSRD Technical Report 1584, October 2000. - Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
2nd Workshop on Intelligent Memory Systems, November 2000.
It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001. - Adaptively Mapping Code in an Intelligent Memory Architecture
by Yan Solihin, Jaejin Lee, and Josep Torrellas,
2nd Workshop on Intelligent Memory Systems, November 2000.
It also appears in Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001. - FlexRAM Architecture Design Parameters
by Seung-Moon Yoo, Jose Renau, Michael Huang, and Josep Torrellas,
Center for Supercomputing Research and Development (CSRD) Technical Report 1584, October 2000. - Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation
by Qiang Cao, Josep Torrellas, and H. V. Jagadish
International Conference on Computer Design (ICCD), September 2000. - SmartApps: An Application-Centric Approach to High Performance Computing
by Lawrence Rauchwerger, Nancy Amato, and Josep Torrellas,
Thirteen International Workshop on Languages and Compilers for Parallel Computing (LCPC), August 2000. - Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems
by Marcelo Cintra, José F. Martínez and Josep Torrellas,
27th Annual International Symposium on Computer Architecture (ISCA), June 2000. [Presentation slides] - Toward a Cost-Effective DSM Organization that Exploits Processor-Memory Integration
by Josep Torrellas, Liuxi Yang and Anthony-Trung Nguyen,
Sixth International Symposium on High-Performance Computer Architecture (HPCA), January 2000. - Comprehensive Hardware and Software Support for Operating Systems to Exploit MP Memory Hierarchies
by Chun Xia and Josep Torrellas,
IEEE Transactions on Computers, May 1999. - A Chip Multiprocessor Architecture with Speculative Multithreading
by Venkata Krishnan and Josep Torrellas,
IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999. - Excel-NUMA: Toward Programmability, Simplicity, and High Performance
by Zheng Zhang, Marcelo Cintra, and Josep Torrellas,
IEEE Transactions on Computers, Special Issue on Cache Memory, February 1999.
A longer version is CSRD Technical Report 1544, November 1996. - FlexRAM: Toward an Advanced Intelligent Memory System
by Yi Kang, Michael Huang, Seung-Moon Yoo, Zhenzho Ge, Diana Keen, Vinh Lam, Prattap Pattnaik and Josep Torrellas,
International Conference on Computer Design (ICCD), October 1999. [Presentation slides] - Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors
by Yan Solihin, Vinh Lam, and Josep Torrellas,
SC 99, November 1999. [Presentation slides] - The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
by Venkata Krishnan and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1999. - Cache Optimization for Memory-Resident Decision Support Commercial Workloads
by Pedro Trancoso and Josep Torrellas
International Conference on Computer Design (ICCD), October 1999. - Detailed Characterization of a Quad Pentium Pro Server Running TPC-D
by Qiang Cao, Pedro Trancoso, Josep-Lluis Larriba-Pey, Josep Torrellas, Robert Knighten and Youjip Won
International Conference on Computer Design (ICCD), October 1999. - Cache-Only Memory Architectures
by Fredrik Dahlgren and Josep Torrellas,
IEEE Computer Magazine, June 1999. - Optimization of Instruction Fetch for Decision Support Workloads
by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Xavi Serrano, Josep Torrellas, and Mateo Valero,
1999 International Conference on Parallel Processing (ICPP), September 1999. - Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors
by David Koufaty and Josep Torrellas,
1999 International Conference on Parallel Processing (ICPP), September 1999. - Improving the Performance of Bristled CC-NUMA Systems Using Virtual Channels and Adaptivity
by José F. Martínez, Josep Torrellas, and Jose Duato,
1999 ACM International Conference on Supercomputing (ICS), June 1999. - Software Trace Cache
by Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero,
1999 ACM International Conference on Supercomputing (ICS), June 1999. - Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
Fifth International Symposium on High-Performance Computer Architecture (HPCA), January 1999. - Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
First Workshop on Parallel Computing for Irregular Applications, held in conjunction with HPCA-5, January 1999. - Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability
by Josep Torrellas,
Ninth SIAM Conference on Parallel Processing for Scientific Computing, March 1999. - Hardware for Speculative Parallelization in High-End Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
The Third PetaFlop Workshop (TPF-3), February 1999. - Computer Architecture Education at the University of Illinois
by Josep Torrellas,
IEEE Computer Architecture Technical Committee Newsletter, February 1999. - Optimizing the Instruction Cache Performance of the Operating System
by Josep Torrellas, Chun Xia and Russell Daigle,
IEEE Transactions on Computers, December 1998.
A shorter version appeared as
Optimizing Instruction Cache Performance for Operating System Intensive Workloads
1st International Symposium on High Performance Computer Architecture (HPCA), January 1995. - A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors
by Venkata Krishnan and Josep Torrellas,
International Conference on Parallel Architectures and Compilation Techniques (PACT), October 1998. - Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor
by Venkata Krishnan and Josep Torrellas,
International Conference on Supercomputing (ICS), July 1998. - Comparing Data Forwarding and Prefetching for Communication-Induced Misses in Shared-Memory MPs
by David Koufaty and Josep Torrellas,
International Conference on Supercomputing (ICS), July 1998. - An IRAM Architecture for Image Analysis and Pattern Recognition
by Yi Kang, Josep Torrellas and Tom Huang,
14th International Conference on Pattern Recognition, 1998. - Executing Sequential Binaries on a Multithreaded Architecture with Speculation Support
by Venkata Krishnan and Josep Torrellas,
Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98), January 1998. - A Clustered Approach to Multithreaded Processors
by Venkata Krishnan and Josep Torrellas,
International Parallel Processing Symposium (IPPS), March 1998. - Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998. - Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
by Sujoy Basu and Josep Torrellas,
Fourth International Symposium on High-Performance Computer Architecture (HPCA), February 1998. - The Performance of the Cedar Multistage Switching Network
by Josep Torrellas and Zheng Zhang,
IEEE Transactions on Parallel and Distributed Systems (TPDS), April 1997.
A shorter version appeared as
The Performance of the Cedar Multistage Switching Network
Supercomputing'94, November 1994. - How Processor-Memory Integration Affects the Design of DSMs
by Liuxi Yang, Anthony-Trung Nguyen, and Josep Torrellas,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997. - Efficient Use of Processing Transistors for Larger On-Chip Storage: Multithreading
by Venkata Krishnan and Josep Torrellas,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, June 1997. - The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors
by Pedro Trancoso, Josep-L. Larriba-Pey, Zheng Zhang, and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997. - Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA
by Zheng Zhang and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997. - Speeding up the Memory Hierarchy in Flat COMA Multiprocessors
by Liuxi Yang and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture (HPCA), January 1997. - Data Forwarding in Scalable Shared-Memory Multiprocessors
by D. A. Koufaty, X. Chen, D. K. Poulsen, and J. Torrellas,
IEEE Transactions on Parallel and Distributed Systems (TPDS), December 1996.
A shorter version appeared as
Data Forwarding in Scalable Shared-Memory Multiprocessors
1995 International Conference on Supercomputing (ICS), July 1995. - The Illinois Aggressive Coma Multiprocessor Project (i-acoma)
by Josep Torrellas and David Padua,
6th Symposium on the Frontiers of Massively Parallel Computing, October 1996. - An Efficient Implementation of Tree-Based Multicast Routing for Distributed Shared-Memory Multiprocessors
by Manuel Perez Malumbres, Jose Duato, and Josep Torrellas,
1996 Symposium on Parallel and Distributed Processing (SPDP), October 1996. - The Augmint Multiprocessor Simulation Toolkit for Intel x86 Architectures,
by Anthony-Trung Nguyen, Maged Michael, Arun Sharma, and Josep Torrellas,
1996 International Conference on Computer Design (ICCD), October 1996. - The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding
by Pedro Trancoso and Josep Torrellas,
1996 International Conference on Parallel Processing (ICPP), August 1996. - Computer Architecture Education at the University of Illinois: Current Status and Some Thoughts,
by Josep Torrellas,
IEEE Computer Architecture Technical Committee Newsletter, June 1996. - Instruction Prefetching of Systems Codes With Layout Optimized for Reduced Cache Misses
by Chun Xia and Josep Torrellas,
23rd International Symposium on Computer Architecture (ISCA), June 1996. - Optimizing the Primary Cache for Parallel Scientific Applications: The Pool Buffer Approach
by Liuxi Yang and Josep Torrellas,
1996 International Conference on Supercomputing (ICS), June 1996. - Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors
by Alain Raynaud, Zheng Zhang, and Josep Torrellas,
Second International Symposium on High-Performance Computer Architecture (HPCA), January 1996. - Improving the Data Cache Performance of Multiprocessor Operating Systems
by Chun Xia and Josep Torrellas,
2nd International Symposium on High Performance Computer Architecture (HPCA), January 1996. - Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors,
by Josep Torrellas, Andrew Tucker and Anoop Gupta,
Journal of Parallel and Distributed Computing (JPDC), February 1995. - Data Forwarding in Scalable Shared-Memory Multiprocessors
by D. A. Koufaty, X. Chen, D. K. Poulsen, and J. Torrellas,
1995 International Conference on Supercomputing (ICS), July 1995. - Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching,
by Zheng Zhang and Josep Torrellas,
22nd International Symposium on Computer Architecture (ISCA), June 1995. - Optimizing Instruction Cache Performance for Operating System Intensive Workloads
by Josep Torrellas, Chun Xia and Russell Daigle,
1st International Symposium on High Performance Computer Architecture (HPCA), January 1995. - Scalable Shared-Memory Architectures: Introduction to MiniTrack,
by Josep Torrellas,
28th Hawaii International Conference on System Sciences (HICSS), January 1995. - False Sharing and Spatial Locality in Multiprocessor Caches,
by Josep Torrellas, Monica S. Lam and John L. Hennessy,
Transactions on Computers, June 1994. - The Performance of the Cedar Multistage Switching Network
by Josep Torrellas and Zheng Zhang,
Supercomputing'94, November 1994. - An Efficient Algorithm for the Run-time Parallelization of DOACROSS Loops
by Ding-Kai Chen, Josep Torrellas and Pen-Chung Yew,
Supercomputing'94, November 1994. - Comparing the Performance and Programmibility of the DASH and Cedar Multiprocessors for Scientific Loads
by Josep Torrellas and David Koufaty, and David Padua,
1994 International Conference on Parallel Processing (ICPP), August 1994. - Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary
by Josep Torrellas, Andrew Tucker, and Anoop Gupta,
1993 ACM Sigmetrics Conference, May 1993. - Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System
by Josep Torrellas, Anoop Gupta, and John Hennessy,
Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 1992. - Estimating the Performance Advantages of Relaxing Consistency in a Shared-Memory Multiprocessor
by Josep Torrellas and John Hennessy,
1990 International Conference on Parallel Processing (ICPP), August 1990. - Shared Data Placement Optimizations to
Reduce Multiprocessor Cache Miss Rates
by Josep Torrellas, Monica Lam, and John Hennessy,
1990 International Conference on Parallel Processing (ICPP), August 1990. - Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared-Memory Multiprocessor
by Josep Torrellas, John Hennessy, and Thierry Weil,
1990 ACM Sigmetrics Conference, May 1990. - Workshops and Technical Reports
- Defensive ML: Defending Architectural
Side-channels with Adversarial Obfuscation
by Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas,
arXiv:2302.01474, February 2023. - Designing a Robust Controller
for Obfuscating a Computer's Power
by Raghavendra Pothukuchi, Sweta Pothukuchi, Petros G. Voulgaris, and Josep Torrellas,
Technical Report, June 2021. - Speculative Taint Tracking (STT): A Formal Analysis
by Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, and Christopher W. Fletcher,
Technical Report, October 2019. - uComplexity: Estimating Processor Design Effort
by Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau,
Technical Report No. UIUCDCS-R-2005-2644, August 2005. - A Brief Description
of the NMP ISA and Benchmarks
by Mingliang Wei, Marc Snir, Josep Torrellas, and R. Brett Tremaine
Technical Report No. UIUCDCS-R-2005-2633, February 2005. - CFlex: A Programming Language for the FlexRAM Intelligent Memory Architecture
by Basilio Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas,
Technical Report UIUCDCS-R-2002-2287, Dept. of Computer Science, UIUC, July 2002. - Speculative Synchronization in Shared-Memory Multiprocessors
by José F. Martínez and Josep Torrellas,
Technical Report UIUCDCS-R-2001-2255, November 2001. - Speculating Past Locks
by José F. Martínez and Josep Torrellas,
CSRD Technical Report, March 2001. - FlexRAM Architecture Design Parameters
by Seung-Moon Yoo, Jose Renau, Michael Huang, and Josep Torrellas,
Center for Supercomputing Research and Development (CSRD) Technical Report 1584, October 2000. - A Unified Approach to Speculative Parallelization of Loops in DSM Multiprocessors
by Y. Zhang, L. Rauchwerger, and J. Torrellas,
CSRD Technical Report 1542, October 1998. - Application-Driven Design of Advanced Intelligent Memory
by Y.Kang, Z.Ge, M.Huang, D.Keen, V.Lam, S.Yoo, P.Pattnaik and J.Torrellas,
CSRD Technical Report, October 1998. - Hardware for Speculative Reduction Parallelization and Optimization in DSM Multiprocessors
by Y. Zhang, L. Rauchwerger, and J. Torrellas,
CSRD Technical Report 1557, December 1998. - Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors
by Y. Solihin, V. Lam and J. Torrellas,
Technical Report 1563, Center for Supercomputing Research and Development, May 1999. - Cache Optimization for Memory-Resident Decision Support Commercial Workloads
by P. Trancoso and J. Torrellas,
Technical Report 1538, Center for Supercomputing Research and Development, June 1998. - Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
by Y. Zhang, L. Rauchwerger, and J. Torrellas,
CSRD Technical Report 1523, July 1997. - Excel-NUMA: Toward Programmability, Simplicity,
and High Performance
by Z. Zhang, M. Cintra, and J. Torrellas,
CSRD Technical Report 1544, November 1996. - Augmint: A Multiprocessor Simulation Environment for Intel x86 Architectures
by A. Sharma, A. Nguyen, M. Michael, J. Carbajal, and J. Torrellas,
CSRD Technical Report 1463, December 1995. - Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors
by J.Torrellas, A.Tucker, and A.Gupta,
Technical Report CSL-TR-92-536, Stanford Univ., August 1992. - Multiprocessor Cache Memory Performance: Characterization and Optimization
by J.Torrellas,
Technical Report CSL-TR-92-545, Stanford Univ., August 1992. - Characterizing the Cache Performance and Synchronization Behavior of a Multiprocessor Operating System
by J.Torrellas, A.Gupta, and J.Hennessy,
Technical Report CSL-TR-92-512, Stanford Univ., January 1992. - Measurement, Analysis, and Improvement of the Cache Behavior of Shared Data in Cache Coherent Multiprocessors
by J.Torrellas, M.Lam, and J.Hennessy,
Technical Report CSL-TR-90-412, Stanford Univ., February 1990. - Estimating the Performance Advantages of Relaxing Consistency in a Shared-Memory Multiprocessor
by J.Torrellas and J.Hennessy,
Technical Report CSL-TN-90-365, Stanford Univ., February 1990. - A Methodology for Modeling Interprocessor Traffic in Shared-Memory Multiprocessors
by J.Torrellas, J.Hennessy, and T.Weil,
Technical Report CSL-TR-89-385, Stanford Univ., July 1989. - Introductory User's Guide to the Architect's Workbench Tools
by J.Torrellas, B.Bray, K.Cuderman, S.Goldschmidt, A.Kobrin, and A.Zimmerman,
Technical Report CSL-TR-88-355, Stanford Univ., May 1988. - Incremental Logic Simulation Using Waveforms
by J.Torrellas,
Masters Thesis, Dept. of Electrical and Computer Engineering, University of Wisconsin - Madison, December 1987. - Incremental Logic Simulation Using Waveforms
by J.Beetem and J.Torrellas,
Technical Report ECE-87-5, Univ. of Wisconsin - Madison, April 1987.
2025:
2024:
2023:
2022:
2021:
2020:
2019:
2018:
2017:
2016:
2015:
2014:
2013:
2012:
2011:
2010:
2009:
2008:
2007:
2006:
2005:
2004:
2003:
2002:
2001:
2000:
1999:
1998:
1997:
1996:
1995:
1994 and Earlier:
Patents
- "Serverless Computing Using Resource Multiplexing",
by Jovan Stojkovic, Hubertus Franke, Tianyin Xu, Josep Torrellas, October 2022. - "Exploiting Spatial Locality to Reduce Refresh Energy in On-Chip eDRAM Modules",
by Aditya B. Agrawal, Amin Ansari, and Josep Torrellas, 2013. - "Exposing Control of Power and Clock Gating for Software",
by Nicholas P. Carter, Joshua B. Fryman, Robert C. Knauerhase, Aditya B. Agrawal, and Josep Torrellas, 2012. - "Architecture Support System and Method for Memory Monitoring",
by Yuanyuan Zhou, Josep Torrellas, and Pin Zhou, US patent number 7,711,988, May 2010.
Editorship of Journals
- Member of the Editorial Board, Communications of the ACM (CACM), July 2017 - Oct 2018.
- Board of Distinguished Reviewers for the ACM TACO journal, 2013 - 2014.
- Associate Editor, ACM Transactions on Architecture and Code Optimization (TACO), March 2003 - January 2006.
- Member of the Editorial Board, IEEE Computer Architecture Letters (CAL), December 2001 - January 2006.
Recent Research Funding
- Aug 2023 $5 M, NSF, lead PI: J. Torrellas, num PIs: 10, duration: 5 years. Title: PPoSS: LARGE: General-Purpose Scalable Technologies for Fundamental Graph Problems.
- Aug 2023 $252 K, IBM-Illinois Discovery Accelerator Institute, lead PI: J. Torrellas, num PIs: 2, duration: 2 years. Title: High-performance and Energy-efficient Platform Support for Serverless and AI/ML Applications.
- Jan 2023 $39.6 M, SRC and DARPA through JUMP 2.0, lead PI: J. Torrellas, num PIs: 21, duration: 5 years. Title: The ACE Center for Evolvable Computing.
- Jun 2022, $600 K, Intel, lead PI: J. Torrellas, num PIs: 3, duration: 3 years. Title: 2030 Server Architecture for Terabyte-Scale Heterogeneous Computing and Memory.
- Apr 2022, $15 M, NSF Expeditions in Computing, lead PI: M. Gazzola, num PIs: 15, duration: 7 years. Title: Mind in vitro - Computing with Living Neurons.
- Dec 2021, $100 K, Mr. Bruce Ge Fund, lead PI: J. Torrellas, num PIs: 1. Title: Improving Computer Systems.
- Aug 2021, $435 K, Intel, lead PI: J. Torrellas, num PIs: 2, duration: 3 years. Title: Many-domain Processors: Isolation Strategies and their Composability.
- Aug 2021 $369 K, IBM-Illinois Discovery Accelerator Institute, lead PI: J. Torrellas, num PIs: 2, duration: 2 years. Title: Operating System Support for Container Security and Processor Design for Containers.
- Aug 2021 $189 K, IBM-Illinois Discovery Accelerator Institute, lead PI: J. Torrellas, num PIs: 1, duration: 2 years. Title: Accelerator for Irregular Computations.
- Aug 2021 $432 K, IBM-Illinois Discovery Accelerator Institute, lead PI: N. Kim, num PIs: 2, duration: 2 years. Title: Data-driven Energy-efficient Hybrid Cloud with Renewable Energy.
- Jul 2021, $1.2 M, NSF CCF, lead PI: J. Torrellas, num PIs: 2, duration: 4 years. Title: SHF: Medium: Cross-Cutting Effort to Make Non-Volatile Memories Truly Usable.
- Jun 2021, $200 M, IBM+UIUC+State of Illinois, lead PI: D. Chen, num PIs: 15, duration: 10 years. Title: Discovery Accelerator Institute.
- Feb 2021, $160 K, Intel, lead PI: J. Torrellas, num PIs: 1, duration: 2 years. Title: Accelerating Graph Neural Networks (GNNs) on CPUs.
- Oct 2020, $850 K, NSF CSR, lead PI: J. Torrellas, num PIs: 2, duration: 3 years. Title: CNS Core: Medium: Rethinking Architecture and Operating Systems for Modern Virtualization Technologies.
- Oct 2020, $250 K, NSF PPoSS, lead PI: J. Torrellas, num PIs: 4, duration: 3 years. Title: A Cross-Layer Approach to Speed-up Very Large Graph Applications on Distributed Platforms.
- Oct 2020, $210 K, Semiconductor Research Corporation, lead PI: J. Torrellas, num PIs: 3, duration: 3 years. Title: Thwarting Microarchitectural Replay Attacks.
- Mar 2020, $53 K, Google Faculty Research Award, lead PI: C. Fletcher, num PIs: 2. Title: Techniques to Improve Software Defenses Against Spectre Attacks.
- Sep 2018, $1.5 M, Intel, lead PI: C. Fletcher, num PIs: 5. Title: Intel Strategic Research Alliance (ISRA) Center: InvisiSpec: Invisible Speculation for Secure and Efficient Speculative Execution.
- Aug 2018, $1.2 M, NSF CSR, lead PI: J. Torrellas, num PIs: 3. Title: Effective Control to Maximize Resource Efficiency in Large Clusters: Hardware, Runtime, and Compiler Perspectives.
- Sep 2017, $500 K, NSF SPX, lead PI: J. Torrellas, num PIs: 2. Title: Training of Deep Neural Networks Using Shared-Memory Platforms.
- Nov 2016, $260 K, SK Hynix, lead PI: J. Torrellas, num PIs: 1. Title: Page Management in Hybrid DRAM-NVM Memory Systems.
- Aug 2016, $880 K, NSF XPS, lead PI: J. Torrellas, num PIs: 3. Title: XPS:FULL:Breaking the Scalability Wall of Shared Memory through Fast On-Chip Wireless Communication.
- Aug 2016, $300 K, NSF CCF, lead PI: J. Torrellas, num PIs: 1. Title: Eager: Technologies for Ultra Energy-Efficient Multicores.
- Aug 2015, $500 K, NSF CCF, lead PI: J. Torrellas, num PIs: 1. Title: Architectures for Scripting Languages.
- Sep 2012, $2.8 M ($1.77M received), DARPA PERFECT, lead PI: J. Torrellas, num PIs: 3. Title: Parameter Variation at NT Voltage: The Power Efficiency versus Resilience Tradeoff.
- Sep 2012, $8.4 M DOE X-Stack + $3.6M cost share, lead PI: S. Borkar, num PIs: 8. Title: Traleika Glacier X-Stack.
- Sep 2012, $100 K, Mr. Bruce Ge Fund, lead PI: J. Torrellas, num PIs: 1. Title: Improving Computer Systems.
- Sep 2011, $2 M Intel, plus $1.6M from the University of Illinois, lead PI: J. Torrellas, num PIs: 6. Title: Illinois-Intel Parallelism Center (I2PC).
- Jul 2011, $430 K, NSF CSR, lead PI: J. Torrellas, num PIs: 1. Title: Framework for Concurrency Debugging.
- Sep 2010, $2.4 M, NSF CCF, lead PI: J. Torrellas, num PIs: 4. Title: Programmable Many-Core for Extreme Scale Computing.
- Jul 2010, $25.8M DARPA UHPC, plus $23.2M from Intel, lead PI: S. Borkar, num PIs: 14. Title: Runnemede: An Architecture for Ubiquitous High Performance Computing.
- Aug 2010, $1.9 M, DOE ASCR, lead PI: J. Torrellas, num PIs: 4. Title: Thrifty: An Exascale Architecture for Energy Proportional Computing.
- May 2010, $70 K, NSF CSR, lead PI: S. King, num PIs: 2. Title: Supplemental on Deterministic Multiprocessor Replay.
- Aug 2009, $23 K, DARPA TCTO, lead PI: J. Torrellas, num PIs: 1. Title: Study on Extreme Scale Multiprocessors.
- Jun 2009, $168 K, NSF CPA, lead PI: J. Torrellas, num PIs: 3. Title: Supplemental on Addressing the Parameter Variation Challenge.
- Feb 2009, $90 K cash + $30 K equipment, Sun Microsystems, lead PI: J. Torrellas, num PIs: 9. Title: UIUC OpenSPARC Center of Excellence.
- Sep 2008, $350 K, NSF CSR, lead PI: S. King, num PIs: 2. Title: Recording and Deterministically Replaying Shared-memory Multiprocessors.
- Mar 2008, $120 K cash + $50 K equipment, Sun Microsystems, lead PI: J. Torrellas, num PIs: 9. Title: UIUC OpenSPARC Center of Excellence.
- Feb 2008, $6M Intel and Microsoft, plus $4.8M from the University of Illinois, lead PI: M. Snir and W. Hwu, num PIs: 15. Title: Universal Parallel Computing Research Center.
- Sep 2007, $890 K, NSF CSR, lead PI: J. Torrellas, num PIs: 5. Title: Novel Programming Models and Architectures to Simplify Parallel Programming.
- Jul 2007, $1,200 K, NSF CPA, lead PI: J. Torrellas, num PIs: 3. Title: Addressing the Parameter-Variation Challenge through a Cross-Disciplinary Architecture, CAD, and Compiler Approach.
- Apr 2007, $360 K, Semiconductor Research Corporation, lead PI: J. Torrellas, num PIs: 2. Title: Timing Faults Due to Parameter Variation.
- Nov 2004, $40 K cash + 25 K equipment, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Speculative Multithreading.
- Nov 2004, $500 K, DOE Extreme Scale Computation, lead PI: J. Nieplocha, num PIs: 6. Title: Scalable Fault Tolerant Runtime and OS.
- Sep 2003, $1,000 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 4. Title: Automatic Detection and Correction of Bugs.
- Jul 2003, $3,000 K, DARPA-IPTO/IBM/UIUC, lead PI: J. Torrellas, num PIs: 4. Title: IBM PERCS High-Productivity Computer System.
- Apr 2003, $14 K, UIUC-CNRS, lead PI: D. Padua, num PIs: 6. Title: Program Optimization.
- Jul 2002, $100 K, DARPA-IPTO/IBM, lead PI: J. Torrellas, num PIs: 3. Title: IBM PERCS High-Productivity Computer System.
- Sep 2002, $500 K, DOD, lead PI: M. Snir, num PIs: 2. Title: Superconducting Switch for Teraflop Architecture.
- Sep 2001, $1,375 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 2. Title: Novel Scalable Simulation.
- Aug 2001, $750 K, NSF-NGS, lead PI: D. Padua, num PIs: 3. Title: Open MP for Networked Computing.
- Aug 2001, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
- Jun 2001, $2,700 K, DARPA-IPTO, lead PI: J. Torrellas, num PIs: 6. Title: Morphable Multithreaded Memory Tiles.
- Sep 2000, $1,900 K, NSF-EIA, lead PI: J. Torrellas, num PIs: 3. Title: FlexRAM: Intelligent Memory Architecture.
- Sep 2000, $500 K, NSF-ITR, lead PI: J. Torrellas, num PIs: 4. Title: Solving the Protein Folding Problem.
- Dec 2000, $750 K, IBM, lead PI: D. Reed, num PIs: 4. Donation of a 16-node SP2 machine.
- Aug 1999, $10 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. HPCA travel grant.
- Sep 1999, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
- Jun 1999, $325 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. Title: New Architectures to Run Commercial Workloads.
- Sep 1999, $15 K, IBM, lead PI: J. Torrellas, num PIs: 1. Joint study.
- Feb 1998, $75 K in cash and $60 K in equip, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Evaluating Database Workloads on Multiprocessors.
- Aug 1997, $25 K, Commission Scientific Exchange USA-Spain, lead PI: J. Larriba, num PIs: 3. Title: Multiprocessor Computer Architectures and Databases.
- Jun 1997, $110 K, IBM, lead PI: J. Torrellas, num PIs: 1. IBM Partnership.
- Jun 1997, $455 K, NSF-MIPS, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
- Jun 1996, $100 K, NSF-ASC, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
- Sep 1995, $1,213K, DARPA-ITO, lead PI: D. Padua, num PIs: 3. Title: Polaris: A Parallelizing Compiler.
Invited Lectures
- "The SRC/DARPA JUMP2.0 ACE Center for Evolvable Computing".
- Semiconductor Research Corporation, December 2023.
- Semiconductor Research Corporation, October 2023.
- Keynote, Intel Multi-university Research Center on Resilient Architectures and Robust Electronics (RARE), October 2023.
- Intel Corporation, September 2023.
- GlobalFoundries, September 2023.
- Intel Corporation, May 2023.
- MICRON, March 2023.
- Semiconductor Research Corporation, February 2023.
- "Research Trends in Processors and Accelerators for the Cloud".
- Microsoft, October 2023.
- IBM Research, July 2023.
- Distinguished Lecture, ECE Department, Iowa State University, February 2023.
- Distinguished Speaker Series, Department of Computer Science, College of William and Mary, September 2022.
- IBM Research, April 2022.
- "Computing Architectures Enabled by Advances in Stacking and Chiplet Technologies.
- SRC/DARPA JUMP2.0 CHIMES Center, July 2023.
- "Cloud Computer Architecture of the Next Decade."
- Belgrade University, Serbia, May 2023.
- Novi Sad University, Serbia, May 2023.
- Kragujevac University, Serbia, May 2023.
- "Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes".
- Intel Corporation, April 2023.
- "Memory-Efficient Hashed Page Tables".
- ArchFest Forum, Intel Corporation, December 2022.
- "Revisiting Processing in Memory Architectures".
- Keynote, PIM2: Combined Tutorial-Workshop on Processing-in-Memory, October 2022.
- "What Keeps Computer Architects Awake at Night".
- New Frontiers Initiative (NFI), NCSA, Urbana, May 2022.
- ECE Distinguished Lecture, George Washington University, March 2022.
- "Pinned Loads: Taming Speculative Loads in Secure Processors".
- "BabelFish: Fusing Address Translations for Containers".
- Intel Corporation, September 2021.
- "Attaining High Performance through Extreme Energy Efficiency".
- Keynote Speech, CCF International Symposium on Advanced Parallel Processing Technology (APPT 2021), December 2021.
- "SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs".
- Open Innovation Day, Samsung Electronics, March 2021.
- "Building Defenses in Processors against Speculation Attacks".
- Yale University, February 2021.
- "Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism".
- ARM Research Summit 2020, September 2020.
- Intel Corporation, July 2020.
- "Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis".
- Intel Corporation, July 2020.
- "Interdisciplinary Research at a Time of Pervasive Changes".
- Keynote at International Symposium on High-Performance Computer Architecture (HPCA), International Conference on Principles and Practice of Parallel Programming (PPoPP), and International Symposium on Code Generation and Optimization (CGO), Febrary 2020.
- "SecDir: A Secure Directory to Defeat Directory Side-Channel Attacks".
- Intel Corporation, April 2019.
- "Computer Architecture Beyond Performance: Security and Programmability".
- University of California, Riverside, CA, October 2019.
- University of Virginia, Charlottesville, VA, February 2019.
- "Extreme Energy-Efficient Computer Architectures".
- Waseda University, Tokyo, Japan, October 2018.
- "Architectural Support for Novel Computing Paradigms".
- Huawei, Santa Clara, CA, August 2018.
- "Toward Extreme-Scale Manycore Architectures".
- Distinguished Speaker, Northeastern University, Boston, MA, February 2018.
- Keynote, at International Conference on High Performance Computing, Data, and Analytics (HiPC), Hyderabad, India, December 2016.
- University of Southern California, CA, October 2016.
- University of Texas, Austin, TX, September 2016.
- SUNY Binghamton, Binghamton, NY, September 2016.
- Seoul National University, Korea, June 2016.
- Keynote, at International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
- Keynote, at Workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware (BPOE), April 2016.
- "WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication".
- ARM Research Summit, September 2016.
- Intel, Extreme Scale Tech. Rev. Mtg, September 2016.
- "CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization".
- Intel, Extreme Scale Tech. Rev. Mtg, May 2016.
- "ScalCore: Designing a Core for Voltage Scalability".
- Intel, Extreme Scale Tech. Rev. Mtg, March 2016.
- "Improving JavaScript Performance".
- Intel Laboratories, Santa Clara, CA, April 2014.
- "Toward Programmable High-Performance Multicores".
- University of Washington, Seattle, WA, January 2015.
- Stanford University, Stanford, CA, May 2014.
- Qualcomm Research, San Jose, CA, December 2013.
- University of Cyprus, Nicosia, Cyprus, July 2013.
- Technion, Haifa, Israel, June 2013.
- Intel Haifa, Israel, June 2013.
- Princeton University, April 2013.
- Harvard University, April 2013.
- Massachussets Institute of Technology, April 2013.
- University of California Berkeley, April 2013.
- Intel Laboratories, Santa Clara, CA, April 2013.
- Carnegie-Mellon University, April 2013.
- "Boosting the Energy Efficiency of Low-Voltage Multicores".
- Qualcomm, San Diego, CA, August 2014.
- Qualcomm, Raleigh, NC, February 2014.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, January 2014.
- AMD, Austin, TX, December 2013.
- Intel, Hillsboro, OR, December 2013.
- "Tackling Parameter Variation from an Architectural Perspective".
- Keynote, at International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, October 2014.
- "Extreme Scale Computer Architecture: Energy Efficiency from the Ground Up".
- Keynote, at Workshop on Architectures and Systems for Big Data (ASBD), June 2014.
- Office of Technology Management, University of Illinois, October 2013.
- Keynote, IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), George Washington University Virginia Science and Technology Campus, VA, June 2013.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, February 2013.
- Invited Speaker, Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH), Shenzhen, China, February 2013.
- Shanghai Jiao Tong University, Shanghai, February 2013.
- National University of Defense Technology (NUDT), Changsha, China, February 2013.
- Institute for Computing Technology, Chinese Academy of Sciences, Beijing, December 2012.
- Beihang University, Beijing, December 2012.
- Tsinghua University, Beijing, December 2012.
- Pekin University, Beijing, December 2012.
- Keynote, Workshop on Near-Threshold Computing (NTC), Vancouver, Canada, December 2012.
- Jon Postel Distinguished Lecture, Computer Science Department, UCLA, November 2012.
- "Vulcan: Hardware Support for Detecting Sequential Consistency Violations in Programs Dynamically".
- I2PC Distinguished Speaker Series, University of Illinois, September 2012.
- "Low Power Architectural Trends".
- Nortwestern University, October 2011.
- "Novel Techniques to Debug Multithreaded Programs".
- Microsoft Research Asia, Beijing, December 2012.
- Intel Programming Systems Laboratory, October 2010.
- "The Bulk Multicore Architecture for Programmability".
- Seoul National University, Seoul, Korea, September 2011.
- Samsung Advanced Institute of Technology, Seoul, Korea, September 2011.
- KAIST, Daejeon, Korea, September 2011.
- Samsung System LSI division, Seoul, Korea, September 2011.
- Pohang University of Science and Technology, Pohang, Korea, September 2011.
- University of Florida, Gainesville, FL, February 2011.
- University of Michigan, Ann Arbor, MI, April 2010.
- Keynote, at 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects, Bangalore, India, January 2010.
- Intel, Bangalore, India, January 2010.
- DARPA-IPTO, Washington, DC, October 2008.
- Stanford University, Stanford, CA, October 2008.
- Intel Laboratories, Hillsboro, OR, October 2008.
- Sun Microsystems, Santa Clara, CA, October 2008.
- UIUC-UPCRC Research Seminar, Urbana, IL, October 2008.
- Microsoft Research, Redmond, WA, September 2008.
- Intel Laboratories, Santa Clara, CA, August 2008.
- Institute for Computing Technology, Chinese Academy of Sciences, Beijing, June 2008.
- Tsinghua University, Beijing, June 2008.
- Beijing University of Aeronautics and Astronautics, Beijing, June 2008.
- Microsoft Research, Beijing, June 2008.
- IBM Research, Beijing, June 2008.
- Intel Laboratories, Barcelona, June 2008.
- Carnegie Mellon University, June 2008.
- University of California Berkeley, May 2008.
- Massachussets Institute of Technology, May 2008.
- Harvard University, May 2008.
- IBM T.J. Watson Research Center, Yorktown, NY, May 2008.
- Texas A&M University, April 2008.
- Georgia Institute of Technology, April 2008.
- University of Texas at Austin, April 2008.
- University of Tokyo, April 2008.
- Rice University, April 2008.
- "Parameter Variation-Tolerant Computer Architectures".
- Distinguished Speaker Colloquium, ECE Department, North Carolina State University, Raleigh, NC, March 2012.
- IBM Research, Austin, TX, February 2011.
- University of Minnesota, Minneapolis, MN, December 2010.
- Intel, Marlborough, MA, January 2009.
- Keynote, at Los Alamos Computer Science Symposium (LACSS), Santa Fe, October 2008.
- Department of Computer Science Distinguished Lectures, UIUC, Urbana, IL, October 2008.
- Keynote, at Workshop on Quality-Aware Design, June 2008.
- Intel Microarchitecture Research Laboratory, Hillsboro, OR, March 2008.
- Invited Talk at IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips X), Yokohama, Japan, April 2007.
- Waseda University, Tokyo, April 2007.
- Invited Talk at Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006.
- Department of Electrical and Computer Engineering, University of Toronto, December 2005.
- VLSI Circuits Seminar, Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, October 2005.
- "An Agenda for Parallel Computer Architecture and Parallel Computing".
- Texas A&M University, April 2009.
- "Practical Deterministic Multiprocessor Replay".
- Intel Laboratories, Santa Clara, CA, December 2009.
- Microsoft, Redmond, WA, April 2009.
- Intel, Hillsboro, OR, April 2009.
- "Designing Multicores for Single-Thread Performance".
- IBM T.J. Watson Research Center, Yorktown, NY, February 2009.
- Sun Microsystems, Santa Clara, CA, December 2008.
- "Speculative Multithreading Architectures".
- Intel Microarchitecture Research Laboratory, Hillsboro, OR, August 2006.
- "A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads".
- IBM PERCS Virtual Seminar, January 2005.
- "Hardware-Supported Data Race Detection".
- Intel, Champaign, IL, April 2005.
- Intel, Champaign, IL, November 2004.
- "Using Thread Level Speculation for Performance and to Enhance Software Debugging and Programmability".
- Cornell University, Ithaca, NY, November 2004.
- SUN Microsystems, Sunnyvale, CA, August 2004.
- Intel, Champaign IL, January 2004.
- Universidad Complutense de Madrid, Spain, June 2003.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, April 2003.
- Intel Microprocessor Research Laboratory, Santa Clara CA, March 2003.
- "Challenging Issues in Speculative Multithreading".
- Carnegie-Mellon University, Pittsburgh PA, December 2002.
- University of Rochester, Rochester NY, December 2002.
- Intel, Marlboro, MA, May 2002.
- Compaq Computer, Shrewsbury, MA, May 2002.
- Universitat Politecnica de Catalunya, Barcelona, Spain, July 2000.
- "FlexRAM: Toward an Advanced Intelligent Memory System".
- Los Alamos National Laboratory, Los Alamos NM, September 2002.
- Purdue University, West Lafayette, IN, April 2002.
- Intel, Champaign IL, December 2001.
- Keynote Speech at XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
- Los Alamos National Laboratory, Los Alamos NM, March 2001.
- Massachusetts Institute of Technology (MIT), February 2001.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, October 2000.
- Universidad Politecnica de Madrid, Spain, January 2000.
- Chalmers University, Gothenburg, Sweden, December 1999.
- Intel Corporation, Hillsboro, OR, November 1999.
- Universitat Politecnica de Catalunya, Barcelona, Spain, August 1999.
- Univeriste de Versailles, France, July 1999.
- DARPA ITO Data Intensive Systems PI Meeting, Del Mar, CA, February 1998.
- "New Research Topics in Computer Architecture".
- Universidad de Zaragoza, Zaragoza, Spain, June 2002.
- "A Framework for Dynamic Energy Efficiency and Temperature Management".
- Universitat Politecnica de Catalunya, Barcelona, December 2000.
- "Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability".
- Institute for Scientific Computing, Aachen, Germany, August 1999.
- "Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors".
- Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
- National Center for Supercomputing Applications (NCSA), Urbana, IL May 1999.
- "New Trends in Computer Architecture and the i-acoma Scalable Multiprocessor Project".
- NEC Corporation, Fuchu City, Japan, September 1999.
- Waseda University, Tokyo, Japan, September 1999.
- University of Houston, Houston, TX, January 1999.
- Universidade de A Corunha, A Coruhna, Spain, December 1998.
- Universidade de Santiago, Santiago, Spain, December 1998.
- Universitat Politecnica de Catalunya, Barcelona, Spain, December 1998.
- New York University, NY, October 1998.
- DARPA, Washington, DC, September 1998.
- NSF, Washington, DC, September 1998.
- the National Center for Supercomputing Applications, Urbana, IL, May 1998.
- Intel Corporation, Hillsboro, OR, April 1998.
- VLSI Circuits Seminar, University of Illinois at Urbana Champaign, April 1998.
- "Efficient Execution of Database Workloads under Deep Memory Hierarchies".
- Pennsylvania State University, State College, PA, November 1998.
- Oracle Corporation, Redwood Shores, CA, February 1998.
- Hewlett Packard Laboratories, Palo Alto, CA, February 1998.
- "New Results in the Illinois Aggressive COMA Multiprocessor Project".
- Los Alamos National Laboratory, Los Alamos NM, May 1998.
- Hewlett Packard Laboratories, Palo Alto, CA, February 1998.
- Texas A\&M University, College Station, TX, January 1998.
- Convex Computer, Dallas, TX, January 1998.
- Northwestern University, Evanston, IL, December 1997.
- University of Washington, Seattle, WA, October 1997.
- Carnegie-Mellon University, Pittsburgh, PA, October 1997.
- Sequent Computers, Hillsboro, OR, April 1997.
- Silicon Graphics, Mountain View, CA, January 1997.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, November 1996.
- "Exploiting Billion-Transistor Chips for Multiprocessing".
- IBM T.J. Watson Research Center, Yorktown Heights, NY, December 1997.
- Reflections/Projections ACM Student Chapter Conference, Urbana, IL, October 1997.
- "The Illinois Aggressive COMA Multiprocessor".
- Department of Computer Science, Tsinghua University, Beijing, China, January 1997.
- University of California-Berkeley, Berkeley, CA, February 1996.
- Stanford University, Stanford, CA, February 1996.
- Tandem Computers, Cupertino, CA, August 1995.
- SUN Microsystems, Mountain View, CA, August 1995.
- Universidad Politecnica de Valencia, Valencia, Spain, June 1995.
- Universite Paul Sabatier, Toulouse, France, June 1995.
- Intel Scalable Systems Division, Intel Corporation, Beaverton, OR, May 1995.
- IBM T.J. Watson Research Center, Yorktown Heights, NY, February 1995.
- Digital Equipment Corporation, Hudson, MA, February 1995.
- Universitat Politecnica de Catalunya, Barcelona, Spain, December 1994.
- "The Performance of the Cedar Multistage Interconnection Network".
- Universitat Politecnica de Catalunya, Barcelona, Spain, December 1993.
- Intel Corporation, December 2021.
Conference Organization. Steering Committee
- Dec 2017 - Dec 2020, IEEE/ACM International Symposium on Microarchitecture (MICRO).
- Jul 2005 - pres., IEEE/ACM International Symposium on Computer Architecture (ISCA).
- Jul 2005 - pres., IEEE International Symposium on High-Performance Computer Architecture (HPCA).
- Apr 2006 - Feb 2008, ACM Symposium on Principles and Practice of Parallel Programming (PPoPP).
- Sep 2005 - Oct 2007, Aug 2014 - Aug 2018, IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT).
Conference Organization. Chair
- Program Chair. The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Edmonton, Canada, August 2014.
- Program Chair. The 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
- Vice-General Chair. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), 2008-present.
- General Co-Chair. International Conference on Network and Parallel Computing (NPC), Shanghai, China, October 2008.
- Technical Papers Co-Chair. IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC07), Reno, NV, November 2007.
- General Chair. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New York, NY, March 2006.
- Program Chair. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
- General Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Saint Louis, MO, September 2005.
- Program Chair. The 11th International Symposium on High-Performance Computer Architecture (HPCA), San Francisco, CA, February 2005.
- Architecture Area Chair. International Conference for High Performance Computing Networks and Storage (SC03), Phoenix, AZ, November 2003.
- Program Vice-Chair for Architecture. The 17th International Parallel and Distributed Processing Symposium (IPDPS), Nice, France, April 2003.
- Vice-Chair of Architecture. The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.
- General Co-Chair. The 6th International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.
- Minitrack Organizer. Minitrack on Scalable Shared-Memory Architectures. The 28th Hawaii International Conference on System Sciences (HICSS), Hawaii, January 1995.
Conference Organization. Program Committee
- International Symposium on Computer Architecture (ISCA): 2024, 2023, 2022, 2021, 2020 (external), 2019 (external), 2017, 2016 (external), 2015 (external), 2013, 2011, 2010, 2009, 2008, 2007, 2006, 2004, 2001.
- International Symposium on High Performance Computer Architecture (HPCA): 2024 (external), 2023, 2019, 2018, 2017, 2016 (external), 2015, 2012, 2011, 2010, 2009, 2008, 2006, 2004, 2003, 2002, 2001, 1999, 1998.
- International Symposium on Microarchitecture (MICRO): 2022 (external), 2021 (external), 2020 (external), 2019 (external), 2017 (external), 2016 (external), 2015 (external), 2012 (external), 2004, 2003.
- International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS): 2022 (external), 2020 (external), 2018 (external), 2017 (external), 2016 (external), 2015 (external), 2014 (external), 2012 (external), 2011 (external), 2010 (external).
- International Conference on Parallel Architectures and Compilation Techniques (PACT): 2018 (external), 2017 (external), 2016, 2011, 2000.
- IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences: May-June 2021, May-June 2020, May-June 2015, May-June 2013, May-June 2012, January-February 2010, January-February 2008.
- International Conference for High Performance Computing Networks and Storage (SC): 2010, 2008, 2005, 2002.
- International Conference on High Performance Embedded Architectures and Compilers (HIPEAC): 2008.
- Symposium on Principles and Practice of Parallel Programming (PPoPP): 2005.
- Industrial Perspectives on Challenges for Next-Generation Computer Systems, International Symposium on High-Performance Computer Architecture (HPCA): 2005.
- Publications Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT): 2004.
- International Conference on Supercomputing (ICS): 2003, 1999, 1997, 1996.
- International Parallel and Distributed Processing Symposium (IPDPS): 2002, 2001, 1998.
- Finance Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT): 2001.
- Tutorials Chair. International Symposium on Computer Architecture (ISCA): 2001.
- Publicity Chair. International Conference on High Performance Computing (HIPC): 2000.
- International Conference on Parallel Processing (ICPP): 2000, 1999, 1998, 1997.
- International Conference on High Performance Computing (HIPC): 1999.
- Symposium on the Frontiers of Massively Parallel Processing: 1999, 1996.
- Workshops Chair. International Symposium on Computer Architecture (ISCA): 1998.
- Sigmetrics Conference: 1998.
- Workshops and Tutorials Chair. International Symposium on High-Performance Computer Architecture (HPCA): 1998.
- Registration Chair. International Computer Performance and Dependability Symposium (ICPDS): 1996.
- International Conference of the Chilean Computer Science Society (ICCCSS): 1995.
- International Conference on Distributed Computing Systems (ICDCS): 1995.
- International Computer Performance and Dependability Symposium (ICPDS): 1995.
- International Conference on Distributed Computing Systems (ICDCS): 1994.
- Registration Chair. International Symposium on Computer Architecture (ISCA): 1994.
Workshop Organization. Chair
- Program Co-Chair. Workshop on "Machine Learning, Artificial Intelligence, and Multi-Domain Operating Environment", Board on Army Research and Development, National Academies Study, May 2020 and August 2020.
- Program Co-Chair. NSF Workshop on "Inter-Disciplinary Research Challenges in Computer Systems", Williamsburg, VA, March 2018.
- Program Co-Chair. Workshop on "Managing Overprovisioned Processors", Salt Lake City, UT, March 2014.
- Program Chair. "2013 Illinois Symposium on Parallelism: Current State of the Field and the Future", Urbana, IL, September 2013.
- Program Co-Chair. Workshop on Advancing Computer Architecture Research (ACAR). "What Now in ILP Research?", Seattle, WA, September 2010.
- Program Co-Chair. Workshop on Advancing Computer Architecture Research (ACAR). "Failure is not an Option: Popular Parallel Programming", San Diego, CA, February 2010.
- Program Co-Chair. Intel/Microsoft/Illinois/Berkeley Universal Parallel Computing Research Center (UPCRC).
- Workshop on Architecture, Santa Clara, CA, August 2011.
- Workshop on Power Issues, Urbana, IL, April 2011.
- Workshop on Architectures for Fine-Grain Synchronization, Redmond, WA, August 2010.
- Workshop on Compilation for Block-Based Architectures, Urbana, IL, March 2010.
- Workshop on Multicore Architectures for Programmability, Hillsboro, OR, August 2009.
- Workshop on Multicore Computer Architecture for 2015, Urbana, IL, February 2009.
- Workshop on Computer Architecture, Santa Clara, CA, August 2008.
- Program Co-Chair. "Indo-US Workshop on Parallelism and the Future of High-Performance Computing", Bangalore, India, January 2010.
- Program Co-Chair. "First Workshop on Architectural and System Support for Improving Software Dependability (ASID)". In conjunction with ASPLOS-XII, San Jose, CA, October 2006.
- Program Co-Chair. "Second Workshop on Memory Performance Issues (WMPI 2002)". In conjunction with ISCA-29, Achorage, Alaska, May 2002.
- Program Co-Chair. "First Workshop on Memory Performance Issues (WMPI 2001)". In conjunction with ISCA-28, Goteborg, Sweden, June 2001.
- Program Co-Chair. "Ninth Workshop on Scalable Shared Memory Multiprocessors". In conjunction with ISCA-27, Vancouver, June 2000.
- Program Co-Chair. "Eighth Workshop on Scalable Shared Memory Multiprocessors". In conjunction with ISCA-26, Atlanta, GA, May 1999.
- Program Co-Chair. "Seventh Workshop on Scalable Shared Memory Multiprocessors". In conjunction with ISCA-25, Barcelona, June 1998.
- Program Co-Chair. "Fourth Workshop on Computer Architecture Evaluation Using Commercial Workloads". In conjunction with HPCA-7, Monterrey, Mexico January 2001.
- Program Co-Chair. "Third Workshop on Computer Architecture Evaluation Using Commercial Workloads". In conjunction with HPCA-6, Toulouse, France January 2000.
- Program Co-Chair. "Second Workshop on Computer Architecture Evaluation Using Commercial Workloads". In conjunction with HPCA-5, Orlando, January 1999.
- Program Co-Chair. "First Workshop on Computer Architecture Evaluation Using Commercial Workloads". In conjunction with HPCA-4, Las Vegas, February 1998.
- Program Chair. Birds-of-a-Feather Session on "Future Machine Architecture and Organization", at the National Computational Science Alliance (NCSA) Alliance'98, Urbana, IL, April 1998.
Workshop Organization. Program Committee
- Workshop on Near-Threshold Computing (WNTC): 2015, 2012.
- Workshop on Determinism and Correctness in Parallel Programming (WODET): 2013.
- Workshop on Hardware Support for Parallel Program Correctness: 2011.
- Workshop on System Effects of Logic Soft Errors (SELSE): 2007, 2006.
- Workshop on Multithreaded Architectures and Applications (MTAAP): 2007.
- Workshop on Power-Aware Computer Systems (PACS): 2003.
- Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC): 2002, 2001, 2000, 1999.
- Workshop on Intelligent Memory Systems: 2000.
Tutorials and Short Courses
- Tutorial on "MCAt: Combining Machine Learning and Control Theory for Computer Architecture" at International Symposium on Microarchitecture (MICRO), October 2019, 1/2 day, http://iacoma.cs.uiuc.edu/mcat/.
- Course on "Parallel Computer Architecture Concepts", at International Spring School on High Performance Computing, San Sebastian/Donostia, Spain, April 2018. 5.25 hours.
- Course on "Modern Shared-Memory Parallel Computer Architecture", at Beihang University, Beijing, China, December 2012. 12 hours.
- Course on "High Performance Computing Architectures -- Trends and Directions", at UIUC Course on High Performance Computing, Singapore, June 2010.
- "Parallel@Illinois Symposium at Singapore", Singapore, June 2010.
- Course on "Multiprocessor Architectures for Speculative Multithreading", at Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), L'Aquila, Italy, July 2008, one week.
- Course on "Boosting Machine Performance with Thread-Level Speculation", at Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.
- Course on "New Technologies in Computer Architecture", at Universidad de Zaragoza, Spain, June 2002.
- Tutorial on "Performance Modeling Using Hardware Counters", at International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.
- Course on "Scalable Shared-Memory Multiprocessors", at Universitat Politecnica de Catalunya, Barcelona, Spain, July 1998.
- Tutorial on "Scalable Shared-Memory Multiprocessors: Architecture and Implementation Issues", at VII Jornadas de Paralelismo, Santiago, Spain, September 1996.
Panels Organized
- "Is There Research Funding Beyond Machine Learning and Quantum?", International Symposium on Computer Architecture (ISCA), June 2021.
- "How Do We Make HPCA Serve the Community Better", International Symposium on High Performance Computer Architecture, February 2019.
- "Broadening Computer Architecture Research: Embracing New Areas to Keep the Field Vibrant", International Symposium on Computer Architecture, June 2011.
- "Extreme Scale Computing: Challenges and Opportunities", International Symposium on High-Performance Computer Architecture and International Conference on Principles and Practice of Parallel Programming, Bangalore, India, January 2010.
- "High-Performance Architecture Research", Indo-US Workshop on Parallelism and the Future of High-Performance Computing, Bangalore, India, January 2010.
- Minipanel on "Speculative Multithreading Architectures", International Symposium on Computer Architecture, Austin, TX, June 2009.
- "How to Build a Useful Thousand-Core Manycore System?", IEEE International Parallel and Distributed Processing Symposium (IPDPS), Rome, Italy, May 2009.
- "Multi-Core and Many-Core: the 5 to 10 Year View", IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, April 2009.
- "Wish List: Architectural Support and Tool Infrastructure for Improving Software Dependability", Workshop on Architectural and System Support for Improving Software Dependability (ASID), in conjunction with ASPLOS-XII, San Jose, CA, October 2006.
- "An Agenda for Computer Architecture Research on Hardware Complexity", Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA-33, Boston, MA, June 2006.
- "Soft Error Rate (SER) Scaling Trends", Workshop on System Effects of Logic Soft Errors (SELSE), Urbana-Champaign, IL, April 2006.
- "New Technologies in Computer Architecture", Dagstuhl Seminar on Performance Analysis and Distributed Computing (PADC), Dagstuhl, Germany, August 2002.
- "What's the Most Critical Challenge is Supporting Multimedia Applications", The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.
- "Designing Scalable Shared-Memory Multiprocessors Using Commodity Microprocessors and OS: NUMA vs COMA Implementation", Fifth Workshop on Scalable Shared-Memory Multiprocessors, Santa Margherita, Italy, June 1995.
Participation in Panels
- "Organizer's panel", Workshop on Revisiting the Review Processes, Orlando, FL, June 2023.
- "Visualize Your Future: Thought Provoking Insights into Computing and the Computing Workforce in the Next Decade", Conference on Visualization & Visual Analytics (VIS), Oklahoma City, October 2022.
- "Processing-in-memory: Lessons Learned and the Road Ahead", PIM2: Combined Tutorial-Workshop on Processing-in-Memory, Chicago, October 2022.
- "Mentors Panel", CIFellows Mentor Webinar, Computing Community Consortium (CCC), October 2021.
- "Demystifying Grad School", The Third Young Architect Workshop (YArch), Virtual, April 2021.
- "How to Get your Packet Seen?", JOBS Workshop, Co-located with MICRO, Virtual, October 2020.
- "Micro-Architectural Mitigations for Transient Execution Attacks", Intel Side Channel Academic Program (SCAP) Workshop, Virtual, September 2020.
- "Architecture and System for Big Data Processing", Workshop on Architectures and Systems for Big Data (ASBD), Minneapolis, MN, June 2014.
- "Future Applications and Challenges for NTC", Workshop on Near-threshold Computing, Minneapolis, MN, June 2014.
- "The Future of Parallelism", 2013 Illinois Symposium on Parallelism: Current State of the Field and the Future, Urbana, IL, September 2013.
- "Research Directions for 21st Century Computer Systems", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Houston, TX, March 2013.
- "Future of Computing Systems", IBM T.J. Watson Research Center, Yorktown Heights, NY, February 2013.
- "Is Reliability the Main Roadblock to Ultra-Low Voltage Operation?", Workshop on Near-threshold Computing (WNTC), Vancouver, Canada, December 2012.
- "Many Core -- Does It Work?", 8th Workshop on Duplicating, Deconstructing, and Debunking (WDDD), Austin, TX, June 2009.
- "How to Place Students in Top-5 Departments", Department of Computer Science, UIUC, April 2009.
- "Silicon Errors in Modern Integrated Circuits: What are the Main Threats", Third Workshop on System Effects of Logic Soft Errors (SELSE-III), Austin, IL, April 2007.
- "Chip Design in the Nano Era", International Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2005.
- "What Are the Important Research Challenges in Temperature-Aware Computer Systems?", Second Workshop on Temperature-Aware Computer Systems, Madison, WI, June 2005.
- "Current and Future Processors", Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.
- "Research Challenges for the Architecture Community in Temperature-Aware Design", First Workshop on Temperature-Aware Computer Systems, Munich, Germany, June 2004.
- "New Architectural Technologies", DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
- "What does the Future Hold for Parallel Languages?", The 16th International Workshop on Languages and Compilers for Parallel Computing, College Station, TX, October 2003.
- "Future Architectures and Programming Models for High Performance Computing", International Symposium on Principles and Practice of Parallel Programming (PPoPP), San Diego, June 2003.
- "Research in Computer Architecture", XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
- "Microprocessor Design Beyond the PC Era: Is There Room for Innovation?", 15th International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, April 2001.
- "What Tools Do We Use to Evaluate Future Memory Systems?", Third Workshop on Computer Architecture Evaluation Using Commercial Workloads, Toulouse, France, January 2000.
- "Findings of the Petaflop Workshops", The 7th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'99), Annapolis, MD, February 1999.
- "Issues in Petaflop Machines", The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
- "Cooperation Between Industry, Academia and Government to Make Commercial Applications Widely Available", Second Workshop on Computer Architecture Evaluation Using Commercial Workloads, Orlando, FL, January 1999.
- "Microbenchmarks: Risk versus Utility", Workshop on Performance Analysis and its Impact on Design (PAID), Barcelona, June 1998.
- "The First Course: Bottom-Up or Top-Down? Which is More Effective?", Fourth Workshop on Computer Architecture Education, Las Vegas, NV, January 1998.
- "Do Academics Require Access to DBMS Source Code in Order To Do Effective Research in the Area of Computer Architecture for Commercial Workloads?",
First Workshop on Computer Architecture Evaluation Using Commercial Workloads, Las Vegas, NV, January 1998. - "Multiprocessor Applications for IRAM", First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
- "Paths to the Petaflops Architecture", The 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers'96), Annapolis, Maryland, October 1996.
- "Shared-Disk, Shared-Nothing, and Shared-Memory Architectures", First Intel Server Forum, Hillsboro OR, June 1996.
- "What are the Minimal Elements of a Computer Engineering or Computer Science Curriculum?", 2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
- "Hot Research Topics in Processor Architecture and in Shared Memory Multiprocessor Architecture", 1st Workshop on Computer Architecture, Paris, France, June 1995.
Talks at Workshops
- "Thwarting Microarchitectural Replay Attacks", at Program Meeting, Hardware Security Research Program, Semiconductor Research Corporation (SRC), December 2020, June 2021.
- "Building Effective Defenses into Processors", at Intel Side Channel Academic Program (SCAP) Workshop, Virtual, September 2020.
- "A Secure Directory to Defeat Directory Side-Channel Attacks", at Intel Side Channel Academic Programme (SCAP) Workshop, Hillsboro, OR, June 2019.
- "AutoPersist: A Java Framework to Program Non-Volatile Memory without Pain", at Runtimes in the Cloud, Phoenix, AZ, June 2019.
- "The Future of Computing: Secure Computing", at Future of Computing Open Mic Night, Phoenix, AZ, June 2019.
- "WiP: Cross-Core Prime+Probe Attacks on Non-inclusive Caches", at Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2018.
- "Toward Extreme-Scale Shared-Memory Architectures", at Workshop on Perspectives of the Future of Computing, Gotheburg, Sweden, May 2018.
- "Defending Against Information Leakage: Computer Architecture Aspects", at NSF Workshop on Side and Covert Channels in Computing Systems, Washington, DC, March 2018.
- "Architectural Support for Novel Computing Paradigms", at Huawei-Illinois Workshop, Champaign, IL, October 2017.
- "What the Parallelism Center Accomplished", at 2013 Illinois Symposium on Parallelism: Current State of the Field and the Future, Urbana, IL, September 2013.
- "Parameter Variation at NT Voltage: The Power Efficiency versus Resilience Tradeoff", at DARPA PERFECT Program Meeting, Arlington, VA, February 2013.
- "The Illinois Parallelism Center", at Microsoft Faculty Summit, Seattle, WA, July 2012.
- "Toward Programmable Extreme Scale Computing", NSF/CISE Workshop on Cross-Layer Power Optimization and Management (CPOM), Los Angeles, CA, February 2012.
- "Thrifty: An Exascale Architecture for Energy-Proportional Computing", at Exascale Research Meeting, DOE Office of Advanced Scientific Computing Research, San Diego, CA, March 2011.
- "Accelerating Single-Thread Execution with Low Design Complexity: The BubbleWrap Approach", at Workshop on Advancing Computer Architecture Research (ACAR), What Now in ILP Research?, Seattle, WA, September 2010.
- "Update on the Bulk Multicore Architecture", at Universal Parallel Computing Research Center (UPCRC) and Illinois Intel Parallelism Center (I2PC) Summits and Workshops: Santa Clara, CA (August 2008); Urbana, IL (February 2009); Hillsboro, OR (August 2009); Urbana, IL (March 2010); Seattle, WA (August 2010); Urbana, IL (April 2011); Santa Clara, CA (August 2011); Hillsboro, OR (December 2011); Seattle, WA (July 2012); Santa Clara, CA (August 2012); Urbana, IL (September 2013).
- "The Architecture Needs to be Designed for Programmability", at Workshop on Advancing Computer Architecture Research (ACAR), Failure is not an Option: Popular Parallel Programming, San Diego, CA, February 2010.
- "High-Speed, Transparent, Scalable Checkpointing", at Intel Workshop on New Memory Technologies, Hillboro, OR, January 2010.
- "Simple Architectural Support to Check for Determinism", at Workshop on Determinism, Seattle, WA, December 2009.
- "The Bulk Compiler", Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Multicore Architectures for Programmability, Hillsboro, OR, August 2009.
- "Extreme Scale Architectures for Programmability", at DARPA-IPTO Workshop on Ubiquitous High Performance Computing, Stanford, CA, August 2009.
- "High-Performance Parallel Computer Architectures", at Workshop on Careers in High Performance Systems Mentoring, Urbana, IL, July 2009.
- "Multiprocessor Architectures for Programmability", at DARPA-IPTO Workshop on Exascale Ubiquitous High Performance Computing, University of Notre Dame, IN, April 2009.
- "The Bulk Multicore Architecture for Programmability", at Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Multicore Computer Architecture for 2015, Urbana, IL, February 2009.
- "The Bulk Multicore Architecture for Programmability", at Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Computer Architecture, Santa Clara, CA, August 2008.
- "How Do We Use 50-Billion Transistors on a Chip?", at Workshop on The 50 Billion Transistor Challenge, IBM T.J. Watson Research Center, Yorktown Heights, NY, July 2008.
- "An Updated Evaluation of ReCycle", at Workshop on Duplicating, Deconstructing, and Debunking, Beijing, China, June 2008.
- "Speculative Multithreaded Architectures", at Workshop on Architectures and Compilers for Multithreading, Indian Institute of Technology, Kanpur, India, December 2007.
- "Terascale-Level Multicore Processor Architectures: Promises and Roadblocks", at Workshop on Terachip Codesign, Defense Science Research Council (DSRC), Arlington, VA, October 2007.
- "Colorama: Supporting the Data-Centric Synchronization Model", at Workshop on Directions in Multi-Core Processor Research, Microsoft Research, Redmont, WA, January 2007.
- "Metrics for Processor Complexity", at Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA, June 2005.
- "Modern Rollback Techniques", at DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design, Menlo Park, CA, February 2005.
- "New Architectural Technologies for Shared-Memory Systems", at DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
- "The FlexRAM Intelligent Memory System", at the Workshop on the Implementation of Multi-PIM Systems (WIMPS), Bodega Bay, CA, February 2002.
- "Hardware for Speculative Parallelization in High-End Multiprocessor", at The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
- "New Multithreading Architectures", at Internal IBM Workshop on Next Generation Processor Architectures, IBM Rochester, Rochester, MN, September 1998.
- "Hardware for Speculative Parallelization in Large- and Small-Scale Multiprocessors", at Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
- "Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors", at Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
- "Computer Architecture Education at the University of Illinois", at 5th Annual Workshop on Computer Architecture Education, Barcelona, Spain, June 1998.
- "COTS-Based Route to Petaflops Systems", at Petaflops Systems Operations Working Review (POWR), Bodega Bay, CA, June 1998.
- "FlexRAM: Advanced Intelligent Memory", at Data Intensive Computing Systems, DARPA PI Meeting, Del Mar, CA, February 1998.
- "How Processor-Memory Integration Affects the Design of DSMs", at First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
- "A COTS-Based Petaflops Design", at 1997 Petaflops Algorithms Workshop (PAL'97), Williamsburg, VA, April 1997.
- "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at Workshop on the Petaflop Frontier, Annapolis MD, October 1996.
- "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at First Intel Server Forum, Hillsboro OR, June 1996.
- "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at Petaflops Architecture Workshop (PAWS'96), Oxnard CA, April 1996.
- "Computer Architecture Education at the University of Illinois: Current Status and Some Thoughts", at 2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
- "The Illinois Aggressive COMA Multiprocessor", at 1st Workshop on Computer Architecture, Paris, France, June 1995.
- "Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors", at Third Workshop on Scalable Shared-Memory Multiprocessors, San Diego, CA, May 1993.
- "The Cache Behavior of Shared Data in Cache-Coherent Multiprocessors", at First Workshop on Scalable Shared-Memory Multiprocessors, Seattle, WA, May 1989.
Participation in Other Workshops and Meetings
- PI Meeting for the Intel Multi-university Research Center on Resilient Architectures and Robust Electronics (RARE), September 2022, October 2023.
- "Mechanism Design for Improving Hardware Security", CCC Workshop, August 2022.
- "Workshop on Redefining the Future of Computer Architecture from First Principles (Arch-1)", NSF, March 2022.
- "MOCHA: ML Optimized Compilers for Heterogeneous Architectures", ISAT/DARPA, December 2021.
- Intel Side Channel Academic Program (SCAP) Workshop, November 2021.
- "DOPLR: Data-Oblivious Interdisciplinary Representation", ISAT/DARPA, Oct. 2020 - May 2021.
- "ARM Research Summit 2020", Virtual, September 2020.
- "Workshop on Digital Computing to Overcome the Limitations of Moore's Law", San Francisco, CA, May 2018.
- "International Roadmap for Devices and Systems (IRDS) Fall Workshop", McLean, VA, November 2017.
- "ARM Research Summit", Cambridge, UK, September 2016.
- "Nanotechnology-Inspired Information Processing Systems Workshop", Washington, DC, August 2016.
- "Computing Beyond 2025 Summit", Argonne National Laboratory, August 2016.
- "Arch2030: A Vision of Computer Architecture Research over the Next 15 Years Workshop", Seoul, Korea, June 2016.
- "CCC Symposium on Computing Research Addressing National Priorities and Societal Needs", Washington, DC, May 2016.
- "Computing Innovation Fellows (CIFellows) Workshop", San Francisco, CA, May 2014.
- "A Day at Technion", Technion, Haifa, Israel, June 2013.
- "30 Years of Parallel Computing at Argonne", Argonne National Laboratory, IL, May 2013.
- "DARPA PERFECT Program Meeting": Arlington, VA, February 2013; Arlington, VA, July 2013; Berkeley CA, January 2014.
- "DOE Exascale Research Conference": San Diego, CA, March 2011; Annapolis, MD, October 2011; Portland, OR, April 2012; Portland, OR, September 2012; Berkeley, CA, March 2013.
- "ACS Productivity Workshop", DOD, Ford Meade, MD, July 2011.
- "Universal Parallel Computing Research Center (UPCRC) and Illinois Intel Parallelism Center (I2PC) Summits and Workshops": Santa Clara, CA (August 2008); Urbana, IL (February 2009); Hillsboro, OR (August 2009); Urbana, IL (March 2010); Seattle, WA (August 2010); Urbana, IL (April 2011); Santa Clara, CA (August 2011); Hillsboro, OR (December 2011); Seattle, WA (July 2012); Santa Clara, CA (August 2012); Urbana, IL (September 2013).
- "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2010.
- "Google Day", San Jose, CA, July 2008.
- "Research@Intel Day", Mountain View, CA, June 2008.
- "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2008.
- "DOE/DOD Workshop on Emerging High Performance Architectures & Applications", Washington, DC, November 2007.
- "Workshop on Computer Academic/Industry Architecture Consortium (CAIAC)", Austin, TX, September 2007.
- "Microsoft Faculty Summit", Redmond, WA, July 2007.
- "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2006.
- "Computing Research Associtation (CRA) Conference on Grand Research Challenges: Revitalizing Computer Architecture Research", Monterey Bay, CA, December 2005.
- "Intel Multi-Core University Research Conference", Portland, OR, December 2005.
- "NSF-CISE Area Review. Area of Computer Architecture and Organization", NSF, May 2005.
- "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2005.
- "DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design", Menlo Park, CA, February 2005.
- "Meeting of Lead PIs of Medium and Large Projects in the Information Technology Research (ITR) NSF Program", Washington, June 2004.
- "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2004.
- "Workshop on Software for Processor-In-Memory Based Parallel Systems", San Jose, CA, March 2004.
- "Science Case for Large-scale Simulation," DOE Workshop, Washington, June 2003.
- "Review Panel of the Programa Ramon y Cajal for Returning Scientists", Government of Spain, Madrid, June 2003.
- "Performance Analysis and Distributed Computing (PADC 2002)", Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
- "Performance Engineering Technology & Research Sponsored Under the NSF Next Generation Software Program", Austin, TX, February 2002.
- "Workshop on the Implementation of Multi-PIM Systems (WIMPS)", Bodega Bay, CA, February 2002.
- "Review Panel of the Programa Ramon y Cajal for Returning Scientists", Government of Spain, Madrid, September 2001.
- "All Hands NCSA Meeting", Urbana, IL, May 2001.
- "NSF-CCR Workshop on Research Directions for Next-Generation Systems Design and Integration", Seattle, WA, June 1999.
- "NCSA Alliance Technical Working Meeting", Oak Brooks, IL, May 1999.
- "The Third PetaFlop Workshop (TPF-3)", Annapolis, MD, February 1999.
- "IBM Workshop on Next Generation Processor Architectures", IBM Rochester, Rochester, MN, September 1998.
- "Petaflops Systems Operations Working Review (POWR)", Bodega Bay, CA, June 1998.
- "Research Workshop between the University of Illinois at Urbana-Champaign and the Centre National de la Recherche Scientifique (CNRS) of France", Urbana, IL, April 1998.
- "National Computational Science Alliance (NCSA) Alliance'98 Conference", Urbana, IL, April 1998.
- "Petaflops Algorithms Workshop (PAL'97)", Williamsburg, VA, April 1997.
- "Workshop on the Petaflop Frontier", Annapolis MD, October 1996.
- "DARPA ITO General PI Meeting", Dallas, TX, October 1996
- "DARPA Workshop on Performance Evaluation", Washington DC, September 1996.
- "NSF Experimental Research Workshop", Washington DC, June 1996.
- "Petasoft: Software for Petaflop Machines", Bodega Bay CA, June 1996.
- "First Intel Server Forum", Hillsboro OR, June 1996.
- "PetaFlops Architecture Workshop PAWS'96", Oxnard CA, April 1996
- "1st Workshop on Computer Architecture", Paris, France, June 1995.
Postdoctoral Researchers, M.S. Students, and Visitors
- Postdoctoral Researchers
- Chloe Alverti, Sept 2023 - Sept 2025, from National Technical University of Athens.
- Nurani Saoda, Sept 2023 - Sept 2025, from University of Virginia.
- Sanyam Mehta, Oct 2014 - Aug 2015, University of Minnesota, USA
- Wonsun Ahn, Apr 2012 - Aug 2014, University of Illinois, USA
- Amin Ansari, Sep 2011 - Aug 2013, University of Michigan, USA
- Wei Liu, Aug 2001 - Aug 2006, Tsinghua University, China
- Basilio Fraguela, Aug 2001 - Aug 2002, Universidade A Coruna, Spain
- Granted M.S. Degrees:
- Russell Daigle, Xiangfeng Chen, David Oesterreich, Alain Raynaud, Kittipong Mungnirun, Pedro Trancoso, Arun Sharma, Jovan Mitrevski, Jose Martinez, Zhenzhou Ge, Michael Huang, Yan Solihin, Jose Renau, Milos Prvulovic, Vinh Lam, James Tuck, Kuan Chen, Smruti Sarangi, Radu Teodorescu, Paul Sack, Brian Greskamp, Pablo Montesinos, Abdullah Muzahid, Ulya Karpuzcu, Shanxiang Qi, Rishi Agarwal, Marios Nicolaides, Ben Ahrens, Raghavendra Pothukuchi, Mengjia Yan, Tanmay Gangwani, Dimitrios Skarlatos, Ali Bohloolizamani, Yasser Shalabi, Apostolos Kokolis, Azin Heidarshenas, Antonio Franques-Garcia ("Fuzzy-Token: An adaptive MAC protocol for wireless network-on-chip"), Namrata Mantri ("Flexible Cuckoo Directory to Protect Against Side Channel Attacks"), Houxiang Ji ("Demystifying Graph Neural Networks in Recommender Systems").
- Visiting Scientists
- Bernat Olle, Mar 2024 - Sep 2024, Universitat Politecnica de Catalunya, Spain.
- Adrian Marruedo, Feb 2018 - Sep 2018, Universitat Politecnica de Catalunya, Spain.
- Xavier Timoneda, Apr 2017 - Sep 2017, Universitat Politecnica de Catalunya, Spain.
- Oscar Plata, Sep 2015 - Nov 2015, Universidad de Malaga, Spain.
- Sonia Gonzalez, Sep 2015 - Nov 2015, Universidad de Malaga, Spain.
- Sergi Abadal, May 2015 - Nov 2015, Universitat Politecnica de Catalunya, Spain.
- Benjamin Sanhelices, Aug 2010 - Dec 2010, Universidad de Valladolid, Spain.
- Lois Orosa, Sep 2009 - Dec 2009, Universidad de Santiago, Spain.
- Norimasa Otsuki, Aug 2009 - Aug 2010, Renesas Technology, Japan.
- Dario Suarez, May 2008 - Jul 2008, Universidad de Zaragoza, Spain
- Daniel Chaver, Jul 2002 - Aug 2002, Universidad Complutense de Madrid, Spain
- Keiji Kimura, Aug 2001 - Oct 2001, Waseda University, Japan
- Pedro Trancoso, Jul 2000 - Aug 2000, International College, Limassol, Cyprus
- Jaejin Lee, Aug 1999 - Dec 1999, Michigan State University, MI
- Paul Feautrier, Feb 1999 - May 1999, Universite de Versailles, Versailles, France
- Diego Llanos, May 1999 - Jul 1999, Universidad de Valladolid, Valladolid, Spain
- Josep Lluis Larriba-Pey, Apr 1996 - Sep 1996, Jul 1997 - Sep 1997, Universitat Politecnica de Catalunya, Barcelona, Spain
Teaching Activity
- Extensive teaching and advising experience at the undergraduate and graduate levels. Taught undergraduate- and graduate-level courses on computer architecture, computer organization, and logic design at UIUC.
- Invited to talk about "Computer Architecture Education at the University of Illinois" at the 2nd, 4th, and 5th Annual Workshop on Computer Architecture Education, February 1996, January 1998, and June 1998.
- Appeared in the local student newspaper Daily Illini under "Incomplete List of Teachers Ranked Excellent By Their Students" (Fall 1995, Spring 1995, Fall 1998, Spring 2018, Fall 2018, Spring 2019, Fall 2019, Spring 2021).
- Some of the courses taught were being broadcasted to large off-campus audiences, both in the U.S. and in India.
- Organized the weekly Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Seminar (August 2011 - August 2013) and invited many Intel personnel to speak.
- Created a graduate-level weekly research seminar: "Research Topics in Advanced Computer Architecture".
- Developed semester-long special-topics courses: "Shared-Memory Multiprocessors: Architecture and Programming" (Spring 93), "Research Issues in New Processor and Memory Architectures" (Spring 01), "Energy-Efficient Computer Architecture" (Fall 2016).
Other Major Service Outside UIUC
- Member, Selection Committee for the HPCA Test of Time Paper Award, 2023-2026.
- Member, IEEE CS Awards Committee for the Technical & Conference Activities Board, 2023.
- Member of the Science and Technology Experts Group (ISTEG), National Academies of Sciences, Engineering, and Medicine, 2021-pres.
- Thesis Defense Opponent for: Wagar Azhar (Chalmers University of Technology, Sweden, March 2022), Christos Sakalis (Uppsala University, Sweden, December 2021).
- Member, ISAT/DARPA "MOCHA: ML Optimized Compilers for Heterogeneous Architectures", 2021.
- Member, ISAT/DARPA "DOPLR: Data-Oblivious Interdisciplinary Representation", Oct. 2020 - May 2021.
- Vice Chair, IEEE Computer Society Fellow Evaluating Committee, 2020.
- Member, External Advisory Board of the WiPLASH European project: "Architecting More Than Moore - Wireless Plasticity for Massive Heterogeneous Computer Architectures", 2020-present.
- Member, External Review Committee of the Computer Science Ph.D. and M.S. programs, College of Computing, Georgia Institute of Technology, Fall 2018.
- Member, Selection Committee for the IEEE Harry Goode Award, 2016, 2017.
- Participant in many NSF, DOE, and DARPA workshops, PI meetings, and program-conception meetings, including DARPA's "Data Intensive Systems", "Bio-Computation", "Polymorphous Computer Architectures", "High Productivity Computer Architectures", "Ubiquitous High Performance Computing", and "Power Efficiency Revolution for Embedded Computing Technology".
- Presented the outcome of Computing Community Consortium (CCC) workshops to CCC, DOE, NSF, AFOSR, and NITRD.
- CCC-appointed liaison to guide the visioning workshops on "Charting the Future of Electronic Design Automation", March 2013, June 2013, and February 2014.
- Member of the Steering Committee, IEEE Computer Society Multicore, April 2013 - pres.
- Member of the IEEE Fellows Selection Committee, 2012, 2013, 2016.
- Member, Computing Innovation Fellows Selection Committee, CCC and CRA, 2010.
- Member, Search Committee for the Editor-in-Chief of the Computer Architecture Letters (CAL) journal, 2005.
- Participant, Site Visit for NSF Expeditions in Computing, December 2015.
- Participant in many NSF Proposal Evaluation Panels: March 1996, November 1998, March 2000, July 2001, February 2002, February 2003, May 2004, August 2004, October 2007, April 2008, December 2008, April 2009, March 2010, December 2010, March 2011, March 2012, May 2013, June 2014, October 2021, January 2024.
- Member of the Advisory Board, Department of Electrical and Computer Engineering, University of Rochester, 2003-pres.
- Member of Enabling Technologies Team A, NSF's National Computational Science Alliance (NCSA) Partnership for an Advanced Computational Infrastructure (PACI), 1997 - 2004.
- I-ACOMA research project was selected as one of the "Eight Point-Design Studies" that DARPA, NSF, NSA and NASA supported in 1996 in a nationwide effort to accelerate the arrival of a petaflop-level machine.
- Regular referee for the major conferences and journals in computer architecture and parallel processing, and reviewer of books on computer architecture.
Major Service Inside UIUC
- Member, ad-hoc committee to advise the Dean on the elevation of the CS Department to a School of Computing, November 2022.
- Guest Speaker at the Video Celebration of Doctoral Graduates, Graduate College, UIUC, December 2020.
- Mentor of multiple Assistant Professors at UIUC's Computer Science Department.
- Member, Computer Science Promotion and Tenure Committee, 2018-2021.
- Member, Graduate Student Mentoring Guidelines Working Group, College of Engineering, 2019.
- Member of the Advisory Board, IBM-Illinois Center for Cognitive Computing Systems Research, April 2016.
- Member, Search Committee for Associate Dean for Graduate, Professional, and Online Education, College of Engineering, March 2016.
- Member of College of Engineering Executive Committee (2002-2008) and Grievance Committee (2002-3, 2006-7).
- Served in many special committees at the College of Engineering.
- Served in many committees at the Department of Computer Science: Promotions and Tenure; Faculty Recruiting; Chairs and Professorships; Faculty and Staff Awards; Advisory; Distinguished Lecture and Departmental Seminar; Fellowships, Assistantships and Graduate Admissions; Computing and Technology Advisory; Task Force on Graduate Student Weekend; Courses and Curriculum; Undergraduate Study; Graduate Advising; Undergraduate Advising; TEI; Graduate Research Orientation; Standing Subcommittee on Engineering/Chemistry Liaison; Computer Affiliates Program; Search Committee for the Director of Budget and Resource Planning; CSL Computing and Networking; and CSRD Industrial Affiliates Program.
- Member, Computer Science Department Head Review Committee, 2015.
- Chair, Architecture, Compilers, and Parallel Computing Area, Department of Computer Science, 2004-2006, 2016-2017, 2020-pres.
- Member, Parallel Computing Institute (PCI) Growth Committee, 2013-pres.
- Host to many speakers and visitors invited to the Department of Computer Science.
- Participated and organized faculty retreats for the Computer Science Department, Computer Engineering, and College of Engineering.
- Participated in several Illinois Computer Science Alumni reunions across the nation.
Other Activities
- Consultant for several companies.
- Consultant for patent assessment. Member of the Round Table Group (RTG) Network of Patent Consultants.