Wei Liu, Ph.D.

 Research Scientist
 Programming Systems Lab
 Intel Corporation

 E-mail: dr.weiliu at gmail.com
 Address:
          2200 Mission College Blvd.
          Santa Clara, CA 95054

Curriculum Vitae: [PDF]

Wei Liu received his B.S. and Ph.D. in Computer Science from Tsinghua University, China, in 1997 and 2001 respectively. He is currently a research scientist in the Programming System Lab at Intel Corporation. Before he joined Intel, he was a research scientist of Computer Science at UIUC working with Prof. Josep Torrellas.

Research Interests:

Computer architecture and compilers for chip multiprocessors. Software and hardware reliability.

Selected Publications    [Completed Paper List]

  Journal Papers

    [IEEE MICRO] Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck and Josep Torrellas
   Energy-Efficient Thread-Level Speculation on a CMP
   IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, Jan-Feb 2006
  
    [ACM TACO] Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu and Josep Torrellas
   Efficient and Flexible Architectural Support for Dynamic Monitoring,
   ACM Transactions on Architecture and Code Optimization (TACO), Volume 2 Issue 1, March 2005
  
    [IEEE MICRO] Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas
   iWatcher: Simple and General Architectural Support for Software Debugging,
   IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, Nov-Dec 2004

  Coference Papers

    [MICRO'06] Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou and Josep Torrellas
   PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
   The 39th Annual IEEE/ACM International Symposium on Micro-architecture (MICRO-39), Dec 2006
  
    [PPoPP'06] Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau and Josep Torrellas
   A TLS Compiler that Exploits Program Structure
   ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Mar 2006
  
    [MICRO'05] Smruti Sarangi, Wei Liu (equal contribution), Josep Torrellas and Yuanyuan Zhou
   ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing,
   The 38th Annual IEEE/ACM International Symposium on Micro-architecture (MICRO-38), Nov 2005.
  
    [P=ac2'05] Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau and Josep Torrellas
   POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure
   The 2nd IBM P=ac2 Conference, Sep 2005
  
    [ICS'05] Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas
   Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation
   ACM International Conference on Supercomputing (ICS), June 2005
  
    [ICS'05] Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas
   Thread-Level Speculation on a CMP Can Be Energy Efficient,
   ACM International Conference on Supercomputing (ICS), June 2005
  
    [MICRO'04] Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Sam Midkiff and Josep Torrellas
   AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-based Invariants,
   The 37th Annual IEEE/ACM International Symposium on Micro-architecture (MICRO-37), Dec 2004
  
    [ISCA'04] Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou and Josep Torrellas
   iWatcher: Efficient Architectural Support for Software Debugging
   The 31st Annual International Symposium on Computer Architecture (ISCA), Munchen, Germany, Jun 19-23, 2004
  

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