About Me

I'm Brian Greskamp, a 27 year old PhD student at the University of Illinois at Urbana-Champaign. My research interests span the field of computer architecture. As an undergraduate and during my first year at UIUC, I focused on using FPGAs to accelerate general-purpose computation. Now I'm working on the complexity and reliability problems of microprocessor design in the nanometer regime. Tomorrow, who knows what I'll be doing... I'm always up for an internship, so check out my resume if you have a challenge for me. Please feel free to flame me at: greskamp-at-uiuc-dot-edu

Incoherent Ramblings

How to go fast on a bicycle
Set the Wayback Machine for 1999 and visit my electronics projects.

Academics

These are final projects for the courses I've taken at UIUC. Note that I consider them to be mostly junk; don't expect any major insights here :-(

Measuring and Characterizing Cache Coherence Traffic
A Value Range Propagation Pass for SUIF
Parallelizing a Simple Chess Program
The Formation and Simulation of a "Whole Program" Gated Singular Assignment PDG
Kernel Selection and Scheduling for Reconfigurable Computing
Linux Whole-System Profiling Study
Resolve-TP: A Resolution Theorem Prover for First Order Logic
Enhanching MLP: A Survey of Runahead Execution and Related Techniques
iPoJ: User-Space Sandboxing for Linux 2.4
LogicSimulator: a Smalltalk environment for teaching introductory digital logic design

Research

Publications

2008

S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects. IEEE Transactions on Semiconductor Manufacturing
S. R. Sarangi, B. Greskamp, A. Tiwari, and J. Torrellas. EVAL: Utilizing Processors with Variation-Induced Timing Errors. To Appear: MICRO 2007

2007

B. Greskamp and J. Torrellas. Paceline: Safely Overclocking to Improve CMP Performance under Parameter Variation. PACT 2007
R. Teodorescu, B. Greskamp, J. Nakano, S. R. Sarangi, A. Tiwari, and J. Torrellas. VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects. 2007 Workshop on Architecture Support for Gigascale Integration
B. Greskamp, S. R. Sarangi, and J. Torrellas. Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. ISCAS 2007
S. R. Sarangi, B. Greskamp, and J. Torrellas. A Model for Timing Errors in Processors with Parameter Variation. ISQED 2007

2006

S. R. Sarangi, B. Greskamp, and J. Torrellas. Rapid Prototyping in Architecture Research using Hardware Hooks in COTS Systems. 2006 Workshop on Architectural Research Prototyping
Brian Greskamp, S. R. Sarangi, and Josep Torrellas. Designing Hardware that Supports Cycle-Accurate Deterministic Replay. 2006 Workshop on Complexity-Effective Design
S. R. Sarangi, B. Greskamp, and J. Torrellas. Cycle Accurate Deterministic Replay for Hardware Debugging. DSN 2006
R. Sass, B. Greskamp, B. Leonard, J. Young, and S. Beeravolu. Online Architectures: A Theoretical Formulation and Experimental Prototype. Journal of Microprocessors and Microsystems Volume 30, Issue 6.

2005

C. Bazeghi, F. J. Martinez, B. Greskamp, J. Torrellas, and J. Renau. uComplexity: Estimating Processor Design Effort. UIUC Tech. Report No. UIUCDCS-R-2005-2644
B. Greskamp, R. Sass. A Virtual Machine for Merit-Based Runtime Reconfiguration. FCCM 2005

2003

Undergrad thesis: A Java Virtual Machine for Runtime Reconfigurable Computing

Unpublished

B. Greskamp. Toward Disciplined Design. An unpublished editorial on the meaning of "complexity" in processor design. October, 2007.

Colleagues and Friends

Eric Cyr: Kung Fu badass mathematician