Held in conjunction with the 29th International Symposium in
Computer Architecture (ISCA 2002)

May 25, 2002
Anchorage, Alaska


Haldun Hadimioglu
Polytechnic University

David Kaeli
Northeastern University

Jeff Kuskin
Atheros Communications

Ashwini Nanda
IBM T.J. Watson Research Center

Josep Torrellas
University of Illinois at Urbana-Champaign

WMPI is a 1-day workshop that provides a forum for researchers and practitioners from academia and industry to discuss advances in computer technology, architecture, software systems, and algorithms that address the growing disparity between memory and CPU/network speeds. Hardware and software techniques that address this performance gap are equally welcome. We are particularly interested in new ideas. Work in early stages of development is encouraged. The workshop will also include one or more keynote speakers.

Possible topics for papers include, but are not limited to:

  • Processors in memory
  • Cache hierarchy organization and coherence
  • RAM architecture and technology
  • Reconfigurable memory systems
  • Intelligent disks
  • Bus/interconnect architectures
  • Network memory
  • Compilation techniques
  • Speculation at the instruction or thread levels
  • Low-power design of memory hierarchies
  • Memory compression
  • Operating system memory management
  • Hardware and software fault tolerance of memory systems
  • Multiprocessing on a single chip
  • Software cache coherence
  • Virtual memory systems


08:00 Breakfast
08:45 Workshop Begins: Welcome Message
09:00 Keynote by Prof. Trevor Mudge - Univ. of Michigan
"Power Aware Memory Issues"
10:00 Break
10:30 Architectural Issues
"Methods for Reducing Memory Latency Penalties in the Next Generation Itanium Processor"
T. Lyon - Hewlett-Packard; C. McNairy - Intel

"LHA: Latency Hiding Algorithm for DRAM"
N. Mekhiel - Ryerson University

"Towards Guided Data Forwarding using Intelligent Memory"
W. Hassanein, and R. Eigenmann - Purdue University; J. Fortes - University of Florida

12:00 Lunch
13:00 Power Issues
"An Analysis of the Potential of Compression in Improving Memory System Performance, Power Consumption and Cost"
N. Mahapatra, J. Liu, and K. Sundaresan - SUNY Buffalo; S. Dangeti and B. Venkatrao - Sun Microsystems

"Adaptive Cache Decay using Formal Feedback Control"
S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron - University of Virginia

"Low-Energy Data Cache Using Sign Compression and Cache Line Bisection"
N.S. Kim, T. Austin, and T. Mudge - Univ. of Michigan

14:30 Multiprocessor and OS Issues
"RH Lock: A Scalable Hierarchical Spin Lock"
Z. Radovic and E. Hagersten - Uppsala University

"Hardware Support for Fast and Bounded-Time Storage Allocation"
S. Donahue, M. Hampton, R. Cytron, and M. Franklin - Washington University; K. Kavi, University of North Texas

15:30 Break
16:00 ILP Issues
"A Day in the Life of a Cache Miss"
T. Karkhanis and J. Smith - University of Wisconsin

"IOP: A Preliminary Study of Instruction-level Object Parallelism for Superscalars"
D. Keen and F. Chong - UC Davis

17:00 Application Issues
"Memory Characterization of the ECperf Benchmark"
M. Karlsson, K. Moore, and E. Hagersten - Uppsala University; D. Wood - University of Wisconsin

"Insights into the Demands of Speech Recognition Algorithms"
R. Krishna, S. Mahlke, and T. Austin - Univ. of Michigan

18:00 Workshop Ends

Last update: April 21 by José F. Martínez