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2nd ANNUAL WORKSHOP ON
MEMORY
PERFORMANCE ISSUES (WMPI 2002)
http://iacoma.cs.uiuc.edu/wmpi2002
Held in conjunction with the 29th
International Symposium in
Computer Architecture (ISCA 2002)
May 25, 2002
Anchorage,
Alaska
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Organizers
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WMPI is a 1-day workshop that provides a forum for
researchers and practitioners from academia and industry to discuss
advances in computer technology, architecture, software systems, and
algorithms that address the growing disparity between memory and
CPU/network speeds. Hardware and software techniques that address this
performance gap are equally welcome. We are particularly interested in new
ideas. Work in early stages of development is encouraged. The workshop
will also include one or more keynote speakers.
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Possible topics for papers include, but are not limited to:
- Processors in memory
- Cache hierarchy organization and coherence
- RAM architecture and technology
- Reconfigurable memory systems
- Intelligent disks
- Bus/interconnect architectures
- Network memory
- Compilation techniques
- Speculation at the instruction or thread levels
- Low-power design of memory hierarchies
- Memory compression
- Operating system memory management
- Hardware and software fault tolerance of memory systems
- Multiprocessing on a single chip
- Software cache coherence
- Virtual memory systems
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FINAL PROGRAM
| 08:00 |
Breakfast
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| 08:45 |
Workshop Begins: Welcome Message
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| 09:00 |
Keynote by Prof. Trevor Mudge - Univ. of Michigan
"Power Aware Memory Issues"
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| 10:00 |
Break
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| 10:30 |
Architectural Issues
"Methods for Reducing Memory Latency Penalties in the Next Generation Itanium Processor"
T. Lyon - Hewlett-Packard; C. McNairy - Intel
"LHA: Latency Hiding Algorithm for DRAM"
N. Mekhiel - Ryerson University
"Towards Guided Data Forwarding using Intelligent Memory"
W. Hassanein, and R. Eigenmann - Purdue University; J. Fortes - University of Florida
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| 12:00 |
Lunch |
| 13:00 |
Power Issues
"An Analysis of the Potential of Compression in Improving Memory System Performance, Power Consumption and Cost"
N. Mahapatra, J. Liu, and K. Sundaresan - SUNY Buffalo; S. Dangeti and B. Venkatrao - Sun Microsystems
"Adaptive Cache Decay using Formal Feedback Control"
S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron - University of Virginia
"Low-Energy Data Cache Using Sign Compression and Cache Line Bisection"
N.S. Kim, T. Austin, and T. Mudge - Univ. of Michigan
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| 14:30 |
Multiprocessor and OS Issues
"RH Lock: A Scalable Hierarchical Spin Lock"
Z. Radovic and E. Hagersten - Uppsala University
"Hardware Support for Fast and Bounded-Time Storage Allocation"
S. Donahue, M. Hampton, R. Cytron, and M. Franklin - Washington University; K. Kavi, University of North Texas
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| 15:30 |
Break |
| 16:00 |
ILP Issues
"A Day in the Life of a Cache Miss"
T. Karkhanis and J. Smith - University of Wisconsin
"IOP: A Preliminary Study of Instruction-level Object Parallelism for Superscalars"
D. Keen and F. Chong - UC Davis
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| 17:00 |
Application Issues
"Memory Characterization of the ECperf Benchmark"
M. Karlsson, K. Moore, and E. Hagersten - Uppsala University; D. Wood - University of Wisconsin
"Insights into the Demands of Speech Recognition Algorithms"
R. Krishna, S. Mahlke, and T. Austin - Univ. of Michigan
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| 18:00 |
Workshop Ends
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Last update: April 21 by José F. Martínez
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