Radu Teodorescu

PhD Candidate
Department of Computer Science at UIUC
Intel Fellow, 2007-2008
Department of Computer Science at UIUC
Intel Fellow, 2007-2008
- « Publications »
- « Curriculum Vitae »
Research Interests:
Microarchitectural solutions to hardware and software reliability challenges.
The effects of parameter variation on microarchitecture.
Selected Publications
- Radu Teodorescu and Josep Torrellas, Variation-Aware Application Scheduling and Power Management for CMPs, 35th International Symposium on Computer Architecture (ISCA), June 2008.
- Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing, 40th International Symposium on Microarchitecture (MICRO), December 2007.
- Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas, VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, Workshop on Architectural Support for Gigascale Integration (ASGI), in conjunction with ISCA, June 2007.
- Pin Zhou, Radu Teodorescu and Yuanyuan Zhou, HARD: Hardware-Assisted Lockset-based Race Detection, International Symposium on High-Performance Computer Architecture (HPCA), February 2007.
- Radu Teodorescu, Jun Nakano and Josep Torrellas, SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback, IEEE Micro Magazine, vol. 26, September/October 2006.
- Radu Teodorescu and Josep Torrellas, Prototyping Architectural Support for Program Rollback Using FPGAs, Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.
Contact Information
Siebel Center for Computer Science, Room 4238University of Illinois
201 N Goodwin
Urbana, IL 61801
Phone (217) 244-2445
E-mail: teodores at cs.uiuc.edu
Homepage: http://iacoma.cs.uiuc.edu/~teodores/