Publications

  1. Aditya Agrawal, Prabhat Jain, Amin Ansari and Josep Torrellas, "Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies," in 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2013. [paper] [presentation] [ieee]
  2. Nicholas Carter, Aditya Agrawal, Shekhar Borkar et al., "Runnemede: An Architecture for Ubiquitous High Performance Computing," in 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2013. [paper] [presentation] [ieee]
  3. Aditya Agrawal, Amin Ansari and Josep Torrellas, "Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules," in 20th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2014. [paper] [presentation] [ieee]
  4. Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal and Asit Mishra, "ScalCore: Designing a Core for Voltage Scalability,” in 22nd IEEE International Symposium on High Performance Computer Architecture (HPCA), March 2016. [paper] [presentation]

Patents

  1. Nicholas Carter, Joshua Fryman, Robert Knauerhase, Aditya Agrawal and Josep Torrellas, “Exposing Control of Power and Clock Gating For Software,” US Patent Pending 13/630738.
  2. Joshua Fryman, Nicholas Carter, Robert Knauerhase, Sebastian Schoenberg and Aditya Agrawal, “Method and Apparatus for Dishonest Hardware Policies,” US Patent Pending 13/630592.
  3. Hung-Yi Liu, Chung-Hsing Wang and Aditya Agrawal, “Robust method for integration of bump cells in semiconductor device design,” US Patent 8239802. [link]