Given that the amount of thread- and instruction-level parallelism of applications vary widely, the traditional CMP approach of statically partitioning the chip resources between threads may lead to wasted resources when one of the threads stalls due to hazards or when the application lacks threads. The Simultaneous Multithreading (SMT)  architecture addresses this problem by allowing complete flexibility in resource sharing. Unfortunately, this approach like the conventional superscalar, is so centralized that it may not be a feasible architecture. In our work, we explore a hybrid approach, namely the clustered SMT architecture. We show that this restricted level of simultaneous multithreading is able to capture most of the performance benefits of the fully centralized approach while, at the same time, allowing the design to be decentralized.

Our work also focuses on simulation methodology. Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven Simulations (EDS). In such environments, the processor component of the system is not fully modeled. With wide-issue superscalar processors being the norm in today's multiprocessor nodes, there is an urgent need for modeling the processor accurately. However, using direct-execution to model a superscalar processor has been considered an open problem. In our work, we propose a novel direct-execution framework that allows accurate simulation of wide-issue superscalar processors without the need for code interpretation. Overall, this approach enables detailed yet fast EDS of superscalar processors for both a uni- and multi-processor configuration.

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