Most Related Publications

1. Evaluation of a Multithreaded Architecture for Cellular Computing
   by C. Cascaval, J. G. Castanos, L. Ceze, M. Denneau, M. Gupta, D. Lieber, J. E. Moreira, K. Strauss and H. S. Warren, Jr
   Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002.

2. Morphable Multithreaded Memory Tiles (M3T) Architecture
   by Jose Renau, James Tuck, Wei Liu, and Josep Torrellas
   University of Illinois UIUC-CS Technical Report, September 2002.

3. Sphinx Parallelization
   by Lee Baugh, Jose Renau, James Tuck, and Josep Torrellas,
   Technical Report, Computer Science Department, University of Illinois, May 2002.

Other Related Publications

1. Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
   by Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia, Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
   Ninth International Symposium on High-Performance Computer Architecture (HPCA), February 2003.

2. Checkpointed Early Resource Recycling in Out-of-order Microprocessors
   by Jose Martinez, Jose Renau, Michael Huang, Milos Prvulovic, and Josep Torrellas,
   35th International Symposium on Microarchitecture (MICRO), November 2002.

3. Speculative Synchronization: Applying Thread-Level Speculation to Parallel Applications
   by Jose Martinez and Josep Torrellas,
   Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.

4. The Design of DEETM: A Framework for Dynamic Energy Efficiency and Temperature Management
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   Journal of Instruction-Level Parallelism (JILP), Vol. 3, 2002.

5. Using a User-Level Memory Thread for Correlation Prefetching
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   29th Annual International Symposium on Computer Architecture (ISCA), May 2002.

6. Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
   by Marcelo Cintra and Josep Torrellas,
   Eigth International Symposium on High-Performance Computer Architecture (HPCA), February 2002.

7. Energy-Efficient Hybrid Wakeup Logic
   by Michael Huang, Jose Renau, and Josep Torrellas,
   International Symposium on Low Power Electronics and Design (ISLPED), August 2002.

8. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
   by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
   Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

9. Automatic Code Mapping on an Intelligent Memory Architecture
   by Yan Solihin, Jaejin Lee, and Josep Torrellas,
   IEEE Transactions on Computers, Special Issue on High Performance Memory Systems, November 2001.

10. Prefetching in an Intelligent Memory Architecture Using a Helper Thread
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    Fifth Workshop on Multithreaded Execution, Architecture, and Compilation, December 2001 (Best Paper Award).

11. Adaptively Mapping Code in an Intelligent Memory Architecture
    by Yan Solihin, Jaejin Lee, and Josep Torrellas,
    Lecture Notes in Computer Science (Vol. 2107) by Springer-Verlag, 2001.

12. L1 Data Cache Decomposition for Energy Efficiency
    by Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas,
    International Symposium on Low Power Electronics and Design (ISLPED), August 2001.

13. Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization
    by Milos Prvulovic, Maria Jesus Garzaran, Lawrence Rauchwerger, and Josep Torrellas,
    28th Annual International Symposium on Computer Architecture (ISCA), June 2001.