Education

Experience

Honors and Awards

Publications

Distributed Software

IEEE TCCA Service

Editorship of Journals

Recent Research Funding

Invited Lectures

Conference Organization. Steering Committee

Conference Organization. Chairman

Conference Organization. Program Committee

Workshop Organization. Chairman

Workshop Organization. Program Committee

Tutorials and Short Courses

Panels Organized

Participation in Panels

Talks at Workshops

By-Invitation Workshops and Meetings

Graduate Students

Postdoctoral Researchers and Visitors

Teaching Activity

Major Service Outside UIUC

Major Service Inside UIUC

Other Activities

Education

  • Ph.D. Electrical Engineering, Stanford University, 1992.
    Dissertation: "Multiprocessor Cache Memory Performance: Characterization and Optimization".
    Advisor: John Hennessy.
  • M.S. Electrical and Computer Engineering, University of Wisconsin-Madison, 1987.
  • B.S. Electrical Engineering, Universitat Politecnica de Catalunya, 1986.

Experience

  • Professor and Willett Faculty Scholar, Computer Science Department, University of Illinois at Urbana-Champaign (UIUC), 8/02-pres.
  • Associate Professor, Computer Science Department, UIUC, 8/98-8/02.
  • Research Staff Member, IBM T.J. Watson Research Center, IBM Research (sabbatical period), 5/98-1/99.
  • Assistant Professor, Computer Science Department, UIUC, 8/92-8/98.
  • Departmental Affiliate, Electrical and Computer Engineering Department, UIUC, 4/93-pres.
  • Senior Computer Systems Engineer, Center for Supercomputing Research and Development (CSRD), UIUC, 9/92-8/94.

Honors and Awards

  • 2006 Best Paper Award, 39th International Symposium on Microarchitecture (MICRO06), December 2006
  • 2006 Paper in IEEE Micro Special Issue: 2006 Micro's Top Picks from Computer Architecture Conferences
  • 2005 Paper in IEEE Micro Special Issue: 2005 Micro's Top Picks from Computer Architecture Conferences
  • 2004 Paper in IEEE Micro Special Issue: 2004 Micro's Top Picks from Computer Architecture Conferences
  • 2004 IEEE Fellow
  • 2003 Paper in IEEE Micro Special Issue: 2003 Micro's Top Picks from Computer Architecture Conferences
  • 2002-pres. Willett Faculty Scholar, UIUC
  • 2001 Best Paper Award, Fifth Workshop on Multithreaded Execution, Architecture, and Compilation
  • 2000 Senior Xerox Award for Outstanding Faculty Research, UIUC
  • 1997-00 IBM Partnership Award
  • 1997 C. W. Gear Outstanding Junior Faculty Award, UIUC
  • 1997 Junior Xerox Award for Outstanding Faculty Research, UIUC
  • 1995,6,8 Intel Research Council Award
  • 1994-9 National Science Foundation Young Investigator Award
  • 1993-6 National Science Foundation Research Initiation Award

Publications

Distributed Software

IEEE TCCA Service

  • Chairman, The Institute of Electrical and Electronics Engineers (IEEE) Technical Committee on Computer Architecture (TCCA), Jul 2005 - pres.

  • Member, Search Committee for the Editor-in-Chief of the Computer Architecture Letters (CAL) journal, 2005.

  • Vice-Chairman, IEEE TCCA, 1998 - Jul 2005.

  • Member of the Advisory Board of the IEEE TCCA, 1998 - Jul 2005.

Editorship of Journals

  • Associate Editor, ACM Transactions on Architecture and Code Optimization (TACO), March 2003 - January 2006.

  • Member of the Editorial Board, IEEE Computer Architecture Letters (CAL), December 2001 - January 2006.

Recent Research Funding

  • Sep 07, $900 K, NSF CSR, lead PI: J. Torrellas, num PIs: 5. Title: Novel Programming Models and Architectures to Simplify Parallel Programming.
  • Jul 07, $1,200 K, NSF CPA, lead PI: J. Torrellas, num PIs: 3. Title: Addressing the Parameter-Variation Challenge through a Cross-Disciplinary Architecture, CAD, and Compiler Approach.
  • Apr 07, $360 K, Semiconductor Research Council, lead PI: J. Torrellas, num PIs: 2. Title: Timing Faults Due to Parameter Variation.
  • Nov 04, $40 K cash + 25 K equipment, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Speculative Multithreading.
  • Nov 04, $500 K, DOE Extreme Scale Computation, lead PI: J. Nieplocha, num PIs: 6. Title: Scalable Fault Tolerant Runtime and OS.
  • Nov 04, $40 K cash + 25 K equipment, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Speculative Multithreading.
  • Sep 03, $1,000 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 4. Title: Automatic Detection and Correction of Bugs.
  • Jul 03, $3,000 K, DARPA-IPTO/IBM/UIUC, lead PI: J. Torrellas, num PIs: 4. Title: IBM PERCS High-Productivity Computer System.
  • Apr 03, $14 K, UIUC-CNRS, lead PI: D. Padua, num PIs: 6. Title: Program Optimization.
  • Jul 02, $100 K, DARPA-IPTO/IBM, lead PI: J. Torrellas, num PIs: 3. Title: IBM PERCS High-Productivity Computer System.
  • Sep 02, $500 K, DOD, lead PI: M. Snir, num PIs: 2. Title: Superconducting Switch for Teraflop Architecture.
  • Sep 01, $1,375 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 2. Title: Novel Scalable Simulation.
  • Aug 01, $750 K, NSF-NGS, lead PI: D. Padua, num PIs: 3. Title: Open MP for Networked Computing.
  • Aug 01, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
  • Jun 01, $2,700 K, DARPA-IPTO, lead PI: J. Torrellas, num PIs: 6. Title: Morphable Multithreaded Memory Tiles.
  • Sep 00, $1,900 K, NSF-EIA, lead PI: J. Torrellas, num PIs: 3. Title: FlexRAM: Intelligent Memory Architecture.
  • Sep 00, $500 K, NSF-ITR, lead PI: J. Torrellas, num PIs: 4. Title: Solving the Protein Folding Problem.
  • Dec 00, $750 K, IBM, lead PI: D. Reed, num PIs: 4. Donation of a 16-node SP2 machine.
  • Aug 99, $10 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. HPCA travel grant.
  • Sep 99, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
  • Jun 99, $325 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. Title: New Architectures to Run Commercial Workloads.
  • Sep 99, $15 K, IBM, lead PI: J. Torrellas, num PIs: 1. Joint study.
  • Feb 98, $75 K in cash and $60 K in equip, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Evaluating Database Workloads on Multiprocessors.
  • Aug 97, $25 K, Commission Scientific Exchange USA-Spain, lead PI: J. Larriba, num PIs: 3. Title: Multiprocessor Computer Architectures and Databases.
  • Jun 97, $110 K, IBM, lead PI: J. Torrellas, num PIs: 1. IBM Partnership.
  • Jun 97, $455 K, NSF-MIPS, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
  • Jun 96, $100 K, NSF-ASC, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
  • Sep 95, $1,213K, DARPA-ITO, lead PI: D. Padua, num PIs: 3. Title: Polaris: A Parallelizing Compiler.

Invited Lectures

  • "Bulk Disambiguation of Speculative Threads in Multiprocessors".

    • At Intel Microarchitecture Research Laboratory, August 2006.

  • "Building Reliable Systems out of Unreliable Components".

    • At Department of Electrical and Computer Engineering, University of Toronto, December 2005.

  • "How Micro-Architects can Help Solve the Problem of Parameter Variation in Upcoming Processor Chips".

    • Invited Talk at IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips X), Yokohama, Japan, April 2007.
    • Invited Talk at Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC206), October 2006.
    • At VLSI Circuits Seminar, Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, October 2005.

  • "A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads".

    • At IBM PERCS Virtual Seminar, January 2005.

  • "Hardware-Supported Data Race Detection".

    • At Intel, Champaign, IL, April 2005.
    • At Intel, Champaign, IL, November 2004.

  • "Using Thread Level Speculation for Performance and to Enhance Software Debugging and Programmability".

    • At Cornell University, Ithaca, NY, November 2004.
    • At SUN Microsystems, Sunnyvale, CA, August 2004.
    • At Intel, Champaign IL, January 2004.
    • At Universidad Complutense de Madrid, Spain, June 2003.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, April 2003.
    • At Intel Microprocessor Research Laboratory, Santa Clara CA, March 2003.

  • "Challenging Issues in Speculative Multithreading".

    • At Carnegie-Mellon University, Pittsburgh PA, December 2002.
    • At University of Rochester, Rochester NY, December 2002.
    • At Intel, Marlboro, MA, May 2002.
    • At Compaq Computer, Shrewsbury, MA, May 2002.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, July 2000.

  • "FlexRAM: Toward an Advanced Intelligent Memory System".

    • At Los Alamos National Laboratory, Los Alamos NM, September 2002.
    • At Purdue University, West Lafayette, IN, April 2002.
    • At Intel, Champaign IL, December 2001.
    • Keynote Speech at XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
    • At Los Alamos National Laboratory, Los Alamos NM, March 2001.
    • At Massachusetts Institute of Technology (MIT), February 2001.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, October 2000.
    • At Universidad Politecnica de Madrid, Spain, January 2000.
    • At Chalmers University, Gothenburg, Sweden, December 1999.
    • At Intel Corporation, Hillsboro, OR, November 1999.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, August 1999.
    • At Univeriste de Versailles, France, July 1999.
    • At DARPA ITO Data Intensive Systems PI Meeting, Del Mar, CA, February 1998.

  • "New Research Topics in Computer Architecture".

    • At Universidad de Zaragoza, Zaragoza, Spain, June 2002.

  • "A Framework for Dynamic Energy Efficiency and Temperature Management".

    • At Universitat Politecnica de Catalunya, Barcelona, December 2000.

  • "Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability".

    • At Institute for Scientific Computing, Aachen, Germany, August 1999.

  • "Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors".

    • At Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
    • At National Center for Supercomputing Applications (NCSA), Urbana, IL May 1999.

  • "New Trends in Computer Architecture and the i-acoma Scalable Multiprocessor Project".

    • At NEC Corporation, Fuchu City, Japan, September 1999.
    • At Waseda University, Tokyo, Japan, September 1999.
    • At University of Houston, Houston, TX, January 1999.
    • At Universidade de A Corunha, A Coruhna, Spain, December 1998.
    • At Universidade de Santiago, Santiago, Spain, December 1998.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1998.
    • At New York University, NY, October 1998.
    • At DARPA, Washington, DC, September 1998.
    • At NSF, Washington, DC, September 1998.
    • At the National Center for Supercomputing Applications, Urbana, IL, May 1998.
    • At Intel Corporation, Hillsboro, OR, April 1998.
    • At VLSI Circuits Seminar, University of Illinois at Urbana Champaign, April 1998.

  • "Efficient Execution of Database Workloads under Deep Memory Hierarchies".

    • At Pennsylvania State University, State College, PA, November 1998.
    • At Oracle Corporation, Redwood Shores, CA, February 1998.
    • At Hewlett Packard Laboratories, Palo Alto, CA, February 1998.

  • "New Results in the Illinois Aggressive COMA Multiprocessor Project".

    • At Los Alamos National Laboratory, Los Alamos NM, May 1998.
    • At Hewlett Packard Laboratories, Palo Alto, CA, February 1998.
    • At Texas A\&M University, College Station, TX, January 1998.
    • At Convex Computer, Dallas, TX, January 1998.
    • At Northwestern University, Evanston, IL, December 1997.
    • At University of Washington, Seattle, WA, October 1997.
    • At Carnegie-Mellon University, Pittsburgh, PA, October 1997.
    • At Sequent Computers, Hillsboro, OR, April 1997.
    • At Silicon Graphics, Mountain View, CA, January 1997.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, November 1996.

  • "Exploiting Billion-Transistor Chips for Multiprocessing".

    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, December 1997.
    • At Reflections/Projections ACM Student Chapter Conference, Urbana, IL, October 1997.

  • "The Illinois Aggressive COMA Multiprocessor".

    • At Department of Computer Science, Tsinghua University, Beijing, China, January 1997.
    • At University of California-Berkeley, Berkeley, CA, February 1996.
    • At Stanford University, Stanford, CA, February 1996.
    • At Tandem Computers, Cupertino, CA, August 1995.
    • At SUN Microsystems, Mountain View, CA, August 1995.
    • At Universidad Politecnica de Valencia, Valencia, Spain, June 1995.
    • At Universite Paul Sabatier, Toulouse, France, June 1995.
    • At Intel Scalable Systems Division, Intel Corporation, Beaverton, OR, May 1995.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, February 1995.
    • At Digital Equipment Corporation, Hudson, MA, February 1995.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1994.

  • "The Performance of the Cedar Multistage Interconnection Network".

    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1993.

  • "The Cache Performance of Multiprocessor Operating Systems".

    • At Hewlett-Packard, Cupertino, CA, May 1992.
    • At Silicon Graphics Inc., Mountain View, CA, January 1992.
    • At SUN Microsystems Computer Corp., Palo Alto, CA, October 1991.

  • "Multiprocessor Cache Memory Performance: Characterization and Optimization".

    • At University of Illinois at Urbana Champaign, May 1992.
    • At University of Texas at Austin, April 1992.
    • At University of California, Los Angeles, April 1992.
    • At New York University, NY, April 1992.

Conference Organization. Steering Committee

  • April 2006 - pres. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP).
  • September 2005 - pres. IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT).
  • July 2005 - pres. IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Conference Organization. Chairman

  • Technical Papers Co-Chair. IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC07), Reno, NV, November 2007.
  • General Chair. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New York, NY, March 2006.
  • Program Chair. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
  • General Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Saint Louis, MO, September 2005.
  • Program Chair. The 11th International Symposium on High-Performance Computer Architecture (HPCA), San Francisco, CA, February 2005.
  • Architecture Area Chair. International Conference for High Performance Computing Networks and Storage (SC03), Phoenix, AZ, November 2003.
  • Program Vice-Chair for Architecture. The 17th International Parallel and Distributed Processing Symposium (IPDPS), Nice, France, April 2003.
  • Vice-Chairman of Architecture. The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.
  • General Co-Chair. The 6th International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.
  • Minitrack Organizer. Minitrack on Scalable Shared-Memory Architectures. The 28th Hawaii International Conference on System Sciences (HICSS), Hawaii, January 1995.

Conference Organization. Program Committee & Other

  • Program Committee Member. The 14th International Symposium on High-Performance Computer Architecture (HPCA), Salt Lake City, UT, February 2008.
  • Program Committee Member. International Conference on High Performance Embedded Architectures and Compilers (HIPEAC), Goteborg, Sweden, January 2008.
  • Program Committee Member. The 34th International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2006.
  • Program Committee Member. The 33rd International Symposium on Computer Architecture (ISCA), Boston, MA, June 2006.
  • Program Committee Member. The 12th International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, February 2006.
  • Technical Papers Committee Member. International Conference for High Performance Computing Networks and Storage (SC05), Seattle, WA, November 2005.
  • Program Committee Member. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Chicago, IL, June 2005.
  • Program Committee Member. Industrial Perspectives on Challenges for Next-Generation Computer Systems, The 11th International Symposium on High-Performance Computer Architecture, (HPCA), San Francisco, CA, February 2005.
  • Program Committee Member. The 37th Annual International Symposium on Microarchitecture (MICRO), Portland, OR, December 2004.
  • Publications Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Antibes, France, September 2004.
  • Program Committee Member. The 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, June 2004.
  • Program Committee Member. The 10th International Symposium on High-Performance Computer Architecture (HPCA), Madrid, February 2004.
  • Program Committee Member. The 36th Annual International Symposium on Microarchitecture (MICRO), San Diego, December 2003.
  • Program Committee Member. The 17th ACM International Conference on Supercomputing (ICS), San Francisco, June 2003.
  • Program Committee Member. The 9th International Symposium on High-Performance Computer Architecture (HPCA), Anaheim, CA, February 2003.
  • Technical Papers Committee Member. International Conference for High Performance Computing Networks and Storage (SC02), Baltimore, MD, November 2002.
  • Program Committee Member. The 8th International Symposium on High-Performance Computer Architecture (HPCA), Boston, February 2002.
  • Program Committee Member. The 16th International Parallel and Distributed Processing Symposium (IPDPS), Fort Lauderdale, FL, April 2002.
  • Finance Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Barcelona, September 2001.
  • Program Committee Member. The 28th Annual International Symposium on Computer Architecture (ISCA), Goteborg, Sweden, June 2001.
  • Tutorials Chairman. The 28th Annual International Symposium on Computer Architecture (ISCA), Goteborg, Sweden, June 2001.
  • Program Committee Member. 15th International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, April 2001.
  • Program Committee Member. The 7th International Symposium on High-Performance Computer Architecture (HPCA), Monterrey, Mexico, January 2001.
  • Publicity Chair. International Conference on High Performance Computing (HIPC), India, December 2000.
  • Program Committee Member. International Conference on Parallel Architectures and Compilation Techniques (PACT), Philadelphia, October 2000.
  • Program Committee Member. The 2000 International Conference on Parallel Processing (ICPP), Toronto, Canada, August 2000.
  • Program Committee Member. The International Conference on High Performance Computing (HIPC99), India, December 1999.
  • Program Committee Member. The 13th ACM International Conference on Supercomputing (ICS), Rhodes, Greece, June 1999.
  • Program Committee Member. The 1999 International Conference on Parallel Processing (ICPP), Aizu-Wakamatsu, Fukushima, Japan, September 1999.
  • Program Committee Member. The 7th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'99), Annapolis, Maryland, February 1999.
  • Program Committee Member. The 5th International Symposium on High-Performance Computer Architecture (HPCA), Orlando, FL, January 1999.
  • Program Committee Member. The 1998 International Conference on Parallel Processing (ICPP), Minneapolis, MN, August 1998.
  • Workshops Chairman. The 25st Annual International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
  • Program Committee Member. The 1998 ACM Sigmetrics Conference, Madison WI, June 1998.
  • Program Committee Member. The 1998 International Parallel Processing Symposium (IPPS), Orlando FL, March 1998.
  • Workshops and Tutorials Chairman. 4th International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, February 1998.
  • Program Committee Member. The 4th International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, February 1998.
  • Program Committee Member. The 1997 International Conference on Parallel Processing (ICPP), Chicago, IL, August 1997.
  • Program Committee Member. The 11th ACM International Conference on Supercomputing (ICS), Vienna, Austria, July 1997.
  • Program Committee Member. The 6th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'96), Annapolis, Maryland, October 1996.
  • Program Committee Member. The 10th ACM International Conference on Supercomputing (ICS), Philadelphia, Pennsylvania, May 1996.
  • Registration Chairman. 2nd International Computer Performance and Dependability Symposium (ICPDS), Urbana IL, September 1996.
  • Program Committee Member. The 15th International Conference of the Chilean Computer Science Society (ICCCSS), Arica, Chile, November 1995.
  • Program Committee Member. The 15th International Conference on Distributed Computing Systems (ICDCS), Vancouver, Canada, May 1995.
  • Program Committee Member. 1st International Computer Performance and Dependability Symposium (ICPDS), Erlangen, Germany, April 1995.
  • Program Committee Member. The 14th International Conference on Distributed Computing Systems (ICDCS), Poznan, Poland, June 1994.
  • Registration Chairman. The 21st Annual International Symposium on Computer Architecture (ISCA), Chicago, IL, April 1994.

Workshop Organization. Chairman

Workshop Organization. Program Committee & Other

  • Program Committee Member. The 3rd Workshop on System Effects of Logic Soft Errors (SELSE-III), Austin, TX, April 2007.
  • Program Committee Member. The 1st Workshop on Multithreaded Architectures and Applications (MTAAP), Long Beach, CA, March 2007.
  • Program Committee Member. The 2nd Workshop on System Effects of Logic Soft Errors (SELSE-II), Urbana-Champaign, IL, April 2006.
  • Program Committee Member. The 3rd Workshop on Power-Aware Computer Systems (PACS), San Diego, December 2003.
  • Program Committee Member. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Istambul, Turkey, November 2002.
  • Program Committee Member. 5th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Austin, December 2001.
  • Program Committee Member. 4th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Monterey, December 2000.
  • Program Committee Member. The 2nd Workshop on Intelligent Memory Systems, Boston, November 2000.
  • Program Committee Member. 3rd Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Toulouse, France, January 2000.
  • Program Committee Member. 2nd Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Orlando, FL, January 1999.

Tutorials and Short Courses

  • Short course on "Boosting Machine Performance with Thread-Level Speculation",
    at Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.

  • Short course on "New Technologies in Computer Architecture",
    at Universidad de Zaragoza, Spain, June 2002.

  • Tutorial on "Performance Modeling Using Hardware Counters",
    at International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.

  • Short course on "Scalable Shared-Memory Multiprocessors",
    at Universitat Politecnica de Catalunya, Barcelona, Spain, July 1998.

  • Tutorial on "Scalable Shared-Memory Multiprocessors: Architecture and Implementation Issues",
    at VII Jornadas de Paralelismo, Santiago, Spain, September 1996.

Panels Organized

  • "Wish List: Architectural Support and Tool Infrastructure for Improving Software Dependability",
    Workshop on Architectural and System Support for Improving Software Dependability (ASID), in conjunction with ASPLOS-XII, San Jose, CA, October 2006.

  • "An Agenda for Computer Architecture Research on Hardware Complexity",
    Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA-33, Boston, MA, June 2006.

  • "Soft Error Rate (SER) Scaling Trends",
    Workshop on System Effects of Logic Soft Errors (SELSE), Urbana-Champaign, IL, April 2006.

  • "New Technologies in Computer Architecture",
    Dagstuhl Seminar on Performance Analysis and Distributed Computing (PADC), Dagstuhl, Germany, August 2002.

  • "What's the Most Critical Challenge is Supporting Multimedia Applications",
    The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.

  • "Designing Scalable Shared-Memory Multiprocessors Using Commodity Microprocessors and OS: NUMA vs COMA Implementation",
    Fifth Workshop on Scalable Shared-Memory Multiprocessors, Santa Margherita, Italy, June 1995.

Participation in Panels

  • "Silicon Errors in Modern Integrated Circuits: What are the Main Threats",
    Third Workshop on System Effects of Logic Soft Errors (SELSE-III), Austin, IL, April 2007.
  • "Chip Design in the Nano Era",
    International Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2005.
  • "What Are the Important Research Challenges in Temperature-Aware Computer Systems?",
    Second Workshop on Temperature-Aware Computer Systems, Madison, WI, June 2005.
  • "Current and Future Processors",
    Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.
  • "Research Challenges for the Architecture Community in Temperature-Aware Design",
    First Workshop on Temperature-Aware Computer Systems, Munich, Germany, June 2004.
  • "New Architectural Technologies",
    DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "What does the Future Hold for Parallel Languages?",
    The 16th International Workshop on Languages and Compilers for Parallel Computing, College Station, TX, October 2003.
  • "Future Architectures and Programming Models for High Performance Computing",
    International Symposium on Principles and Practice of Parallel Programming (PPoPP), San Diego, June 2003.
  • "Research in Computer Architecture",
    XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
  • "Microprocessor Design Beyond the PC Era: Is There Room for Innovation?",
    15th International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, April 2001.
  • "What Tools Do We Use to Evaluate Future Memory Systems?",
    Third Workshop on Computer Architecture Evaluation Using Commercial Workloads, Toulouse, France, January 2000.
  • "Findings of the Petaflop Workshops",
    The 7th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'99), Annapolis, MD, February 1999.
  • "Issues in Petaflop Machines",
    The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
  • "Cooperation Between Industry, Academia and Government to Make Commercial Applications Widely Available",
    Second Workshop on Computer Architecture Evaluation Using Commercial Workloads, Orlando, FL, January 1999.
  • "Microbenchmarks: Risk versus Utility",
    Workshop on Performance Analysis and its Impact on Design (PAID), Barcelona, June 1998.
  • "The First Course: Bottom-Up or Top-Down? Which is More Effective?",
    Fourth Workshop on Computer Architecture Education, Las Vegas, NV, January 1998.
  • "Do Academics Require Access to DBMS Source Code in Order To Do Effective Research in the Area of Computer Architecture for Commercial Workloads?",
    First Workshop on Computer Architecture Evaluation Using Commercial Workloads, Las Vegas, NV, January 1998.
  • "Multiprocessor Applications for IRAM",
    First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
  • "Paths to the Petaflops Architecture",
    The 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers'96), Annapolis, Maryland, October 1996.
  • "Shared-Disk, Shared-Nothing, and Shared-Memory Architectures",
    First Intel Server Forum, Hillsboro OR, June 1996.
  • "What are the Minimal Elements of a Computer Engineering or Computer Science Curriculum?",
    2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
  • "Hot Research Topics in Processor Architecture and in Shared Memory Multiprocessor Architecture",
    1st Workshop on Computer Architecture, Paris, France, June 1995.

Talks at Workshops

  • "Colorama: Supporting the Data-Centric Synchronization Model",
    At Workshop on Directions in Multi-Core Processor Research, Microsoft Research, Redmont, WA, January 2007.
  • "Metrics for Processor Complexity",
    At Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA, June 2005.
  • "Modern Rollback Techniques",
    At DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design, Menlo Park, CA, February 2005.
  • "New Architectural Technologies for Shared-Memory Systems", At DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "The FlexRAM Intelligent Memory System",
    At the Workshop on the Implementation of Multi-PIM Systems (WIMPS), Bodega Bay, CA, February 2002.
  • "Hardware for Speculative Parallelization in High-End Multiprocessor",
    At The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
  • "New Multithreading Architectures",
    At Internal IBM Workshop on Next Generation Processor Architectures, IBM Rochester, Rochester, MN, September 1998.
  • "Hardware for Speculative Parallelization in Large- and Small-Scale Multiprocessors",
    At Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
  • "Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors",
    At Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
  • "Computer Architecture Education at the University of Illinois",
    At 5th Annual Workshop on Computer Architecture Education, Barcelona, Spain, June 1998.
  • "COTS-Based Route to Petaflops Systems",
    At Petaflops Systems Operations Working Review (POWR), Bodega Bay, CA, June 1998.
  • "FlexRAM: Advanced Intelligent Memory",
    At Data Intensive Computing Systems, DARPA PI Meeting, Del Mar, CA, February 1998.
  • "How Processor-Memory Integration Affects the Design of DSMs",
    At First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
  • "A COTS-Based Petaflops Design",
    At 1997 Petaflops Algorithms Workshop (PAL'97), Williamsburg, VA, April 1997.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor",
    At Workshop on the Petaflop Frontier, Annapolis MD, October 1996.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor",
    At First Intel Server Forum, Hillsboro OR, June 1996.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor",
    At Petaflops Architecture Workshop (PAWS'96), Oxnard CA, April 1996.
  • "Computer Architecture Education at the University of Illinois: Current Status and Some Thoughts",
    At 2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
  • "The Illinois Aggressive COMA Multiprocessor",
    At 1st Workshop on Computer Architecture, Paris, France, June 1995.
  • "Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors",
    At Third Workshop on Scalable Shared-Memory Multiprocessors, San Diego, CA, May 1993.
  • "The Cache Behavior of Shared Data in Cache-Coherent Multiprocessors",
    At First Workshop on Scalable Shared-Memory Multiprocessors, Seattle, WA, May 1989.

By-Invitation Workshops and Meetings

  • "Workshop on Directions in Multi-Core Processor Research",
    Microsoft Research, Redmont, WA, January 2007.
  • "DOE Salishan High Speed Computing Conference",
    Salishan Lodge, Gleneden Beach, OR, April 2006.
  • "Computing Research Associtation (CRA) Conference on Grand Research Challenges: Revitalizing Computer Architecture Research",
    Monterey Bay, CA, December 2005.
  • "Intel Multi-Core University Research Conference",
    Portland, OR, December 2005.
  • "NSF-CISE Area Review. Area of Computer Architecture and Organization",
    NSF, May 2005.
  • "DOE Salishan High Speed Computing Conference",
    Salishan Lodge, Gleneden Beach, OR, April 2005.
  • "DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design",
    Menlo Park, CA, February 2005.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, August 2004.
  • "Meeting of Lead PIs of Medium and Large Projects in the Information Technology Research (ITR) NSF Program",
    Washington, June 2004.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, May 2004.
  • "DOE Salishan High Speed Computing Conference",
    Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "Workshop on Software for Processor-In-Memory Based Parallel Systems",
    San Jose, CA, March 2004.
  • "Science Case for Large-scale Simulation,"
    DOE Workshop, Washington, June 2003.
  • "Review Panel of the Programa Ramon y Cajal for Returning Scientists",
    Government of Spain, Madrid, June 2003.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, February 2003.
  • "Performance Analysis and Distributed Computing (PADC 2002)",
    Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
  • "Performance Engineering Technology & Research Sponsored Under the NSF Next Generation Software Program",
    Austin, TX, February 2002.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, February 2002.
  • "Workshop on the Implementation of Multi-PIM Systems (WIMPS)",
    Bodega Bay, CA, February 2002.
  • "Review Panel of the Programa Ramon y Cajal for Returning Scientists",
    Government of Spain, Madrid, September 2001.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, July 2001.
  • "All Hands NCSA Meeting",
    Urbana, IL, May 2001.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, March 2000.
  • "NSF-CCR Workshop on Research Directions for Next-Generation Systems Design and Integration",
    Seattle, WA, June 1999.
  • "NCSA Alliance Technical Working Meeting",
    Oak Brooks, IL, May 1999.
  • "The Third PetaFlop Workshop (TPF-3)",
    Annapolis, MD, February 1999.
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, November 1998.
  • "IBM Workshop on Next Generation Processor Architectures",
    IBM Rochester, Rochester, MN, September 1998.
  • "Petaflops Systems Operations Working Review (POWR)",
    Bodega Bay, CA, June 1998.
  • "Research Workshop between the University of Illinois at Urbana-Champaign and the Centre National de la Recherche Scientifique (CNRS) of France",
    Urbana, IL, April 1998.
  • "National Computational Science Alliance (NCSA) Alliance'98 Conference",
    Urbana, IL, April 1998.
  • "Petaflops Algorithms Workshop (PAL'97)",
    Williamsburg, VA, April 1997.
  • "Workshop on the Petaflop Frontier",
    Annapolis MD, October 1996.
  • "DARPA ITO General PI Meeting",
    Dallas, TX, October 1996
  • "DARPA Workshop on Performance Evaluation",
    Washington DC, September 1996.
  • "NSF Experimental Research Workshop",
    Washington DC, June 1996.
  • "Petasoft: Software for Petaflop Machines",
    Bodega Bay CA, June 1996.
  • "First Intel Server Forum",
    Hillsboro OR, June 1996.
  • "PetaFlops Architecture Workshop PAWS'96",
    Oxnard CA, April 1996
  • "NSF Proposal Evaluation Panel",
    NSF, Washington, DC, March 1996.
  • "1st Workshop on Computer Architecture",
    Paris, France, June 1995.

Graduate Students

  • Granted 23 Ph.D. Degrees:

    • Luis Ceze, 2007
      First Job: Assistant Professor, Department of Computer Science and Engineering, University of Washington, Seattle, WA
      Thesis: "Bulk Operation and Data Coloring for Multiprocessor Programmability"
    • James Tuck, 2007
      First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC
      Thesis: "Efficient Support for Speculative Tasking"
    • Karin Strauss, 2007
      First Job: Member of Research Staff, AMD Laboratories, Seattle, WA
      Thesis: "Cache Coherence in Embedded-Ring Multiprocessors"
    • Smruti R. Sarangi, 2007
      First Job: Member of Technical Staff, Synopsys Inc., Bangalore, India
      Thesis: "Techniques to Mitigate the Effects of Congenital Faults in Processors"
    • Jun Nakano, 2006
      First Job: Member of Research Staff, IBM Research, Tokyo, Japan,
      Thesis: "Techniques to Address Unreliability and Variability of Computing Systems"
    • Jose Renau, 2004
      First Job: Assistant Professor, Department of Computer Engineering, University of California, Santa Cruz
      Thesis: "Chip Multiprocessors with Speculative Multithreading: Design for Performance and Energy Efficiency"
    • Milos Prvulovic, 2003
      First Job: Assistant Professor, College of Computing, Georgia Institute of Technology, Atlanta, GA
      Thesis: "Architectural Support for Reliable Parallel Computing"
    • Jose Martinez, 2002
      First Job: Assistant Professor, Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY
      Thesis: "Speculative Shared-Memory Architectures"
    • Yan Solihin, 2002
      First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC
      Thesis: "Improving Memory Performance Using Intelligent Memory"
    • Michael Huang, 2002
      First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY
      Thesis: "Managing Processor Adaptation for Energy Reduction and Temperature Control"
    • Anthony Nguyen, 2002
      Current Job: Member of Research Staff, Intel Corporation, Santa Clara, CA
      Thesis: "High-Throughput Coherence Controllers"
    • Marcelo Cintra, 2001
      First Job: Lecturer, School of Informatics, University of Edinburgh, UK
      Thesis: "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors"
    • Seung-Moon Yoo, 2001
      First Job: Member of Research Staff, IBM Research, Austin, TX
      Thesis: "Design of Energy-Efficient SOCs with Deep Sub-Micron Circuit Techniques"
    • Qiang Cao, 2000
      First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA
      Thesis: "Performance Characterization and Buffer Memory Optimization of Databases"
    • Sujoy Basu, 2000
      First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA
      Thesis: "Design of Efficient Simple COMA Architectures"
    • Yi Kang, 1999
      First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA
      Thesis: "An Intelligent Memory for Data Intensive Applications"
    • Ye Zhang, 1999
      First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA
      Thesis: "Speculative Parallelization in DSM Multiprocessors"
    • Pedro Trancoso, 1998
      Current Job: Lecturer, Department of Computer Science, University of Cyprus, Cyprus
      Thesis: "Optimizing Memory-Resident DSS Workloads for Caches"
    • Venkata Krishnan, 1998
      First Job: Microprocessor Design Group, DEC Shrewsbury, MA
      Thesis: "Speculative Multithreading Architectures"
    • Liuxi Yang, 1997
      First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA
      Thesis: "Using Advanced Memory Technologies to Build DSM Multiprocessors"
    • David Koufaty, 1997
      First Job: Member of Technical Staff, Intel Corp, Hillsboro, OR
      Thesis: "Compiler Support to Hide Coherence Misses in Shared-Memory Multiprocessors"
    • Zheng Zhang, 1996
      First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA
      Thesis: "Design Alternatives to Reduce Remote Conflict Misses in Shared-Memory Multiprocessors"
    • Chun Xia, 1996
      First Job: Member of Technical Staff, Sun Microsystems, Menlo Park, CA
      Thesis: "Exploiting Multiprocessor Memory Hierarchies for Operating Systems"

  • Currently supervising 9 Students:

    • Wonsun Ahn
    • Luis Ceze
    • Brian Greskamp
    • Pablo Montesinos
    • Smruti Sarangi
    • Karin Strauss
    • Radu Teodorescu
    • James Tuck
    • Abhishek Tiwari

  • Granted 22 M.S. Degrees:

    • Russell Daigle, Xiangfeng Chen, David Oesterreich, Alain Raynaud, Kittipong Mungnirun, Pedro Trancoso, Arun Sharma, Jovan Mitrevski, Jose Martinez, Zhenzhou Ge, Michael Huang, Yan Solihin, Jose Renau, Milos Prvulovic, Vinh Lam, James Tuck, Kuan Chen, Smruti Sarangi, Radu Teodorescu, Paul Sack, Brian Greskamp, Pablo Montesinos.

Postdoctoral Researchers and Visitors

  • Postdoctoral Researchers

    • Dr. Wei Liu, Aug 2001 - Aug 2006
      Tsinghua University, China
    • Prof. Basilio Fraguela, Aug 2001 - Aug 2002
      Universidade A Coruna, Spain

  • Visiting Scientists

    • Daniel Chaver, Jul 2002 - Aug 2002
      Universidad Complutense de Madrid, Spain
    • Dr. Keiji Kimura, Aug 2001 - October 2001
      Waseda University, Japan
    • Prof. Pedro Trancoso, Jul 2000 - Aug 2000
      International College, Limassol, Cyprus
    • Prof. Jaejin Lee, Aug 1999 - Dec 1999
      Michigan State University, MI
    • Prof. Paul Feautrier, Feb 1999 - May 1999
      Universite de Versailles, Versailles, France
    • Diego Llanos, May 1999 - Jul 1999
      Universidad de Valladolid, Valladolid, Spain
    • Maria J. Garzaran, Jan 1999 - Aug 1999, Jan 2000 - Sep 2000, April 2001 - Sep 2001
      Universidad de Zaragoza, Zaragoza, Spain
    • Prof. Josep Lluis Larriba-Pey, Apr 1996 - Sep 1996, Jul 1997 - Sep 1997
      Universitat Politecnica de Catalunya, Barcelona, Spain

Teaching Activity

  • Extensive teaching and advising experience at the undergraduate and graduate levels. Taught undergraduate- and graduate-level courses on computer architecture, computer organization, and logic design at UIUC

  • Invited to talk about "Computer Architecture Education at the University of Illinois" at the 2nd, 4th, and 5th Annual Workshop on Computer Architecture Education, February 1996, January 1998, and June 1998

  • Appeared several times in the local student newspaper Daily Illini under "Incomplete List of Teachers Ranked Excellent By Their Students" (Fall 1995, Spring 1995, and Fall 1998)

  • Some of the courses taught were being broadcasted to large off-campus audiences, both in the U.S. and in India

  • Created a graduate-level weekly research seminar: "Research Topics in Advanced Computer Architecture" (Ongoing since Fall 92)

  • Developed semester-long special-topics courses: "Shared-Memory Multiprocessors: Architecture and Programming" (Spring 93) and "Research Issues in New Processor and Memory Architectures" (Spring 01)

Major Service Outside UIUC

  • Member of the Advisory Board, Department of Electrical and Computer Engineering, University of Rochester, 2003-pres

  • Member of Enabling Technologies Team A, NSF's National Computational Science Alliance (NCSA) Partnership for an Advanced Computational Infrastructure (PACI), 1997-pres

  • I-ACOMA research project was selected as one of the "Eight Point-Design Studies" that DARPA, NSF, NSA and NASA supported in 1996 in a nationwide effort to accelerate the arrival of a petaflop-level machine

  • Participant in many NSF and DARPA workshops, PI meetings, and program-conception meetings, including DARPA's "Data Intensive Systems", "Bio-Computation", "Polymorphous Computer Architectures", and "High Productivity Computer Architectures"

  • Participant in many NSF Proposal Evaluation Panels

  • Participant in proposal evaluation panels for Spain and Canada, 2002, 2003, 2006.

  • External examiner in the Ph.D. defense of P. Machanick, University of Cape Town, South Africa (1996) and M. Karlsson, Chalmers University, Gothenburg, Sweden, (1999)

  • Regular referee of NSF proposals

  • Regular referee for the major conferences and journals in computer architecture and parallel processing

  • Reviewer of books on computer architecture

Major Service Inside UIUC

  • Member of College of Engineering Executive Committee (2002-pres.) and Grievance Committee (2002-3, 2006-7).

  • Served in many committees at the Department of Computer Science: Promotions, Recruiting, Advisory, Distinguished Lecture and Departmental Seminar, Fellowships, Assistantships and Admissions, Computing and Technology Advisory, Task Force on Graduate Student Weekend, Courses and Curriculum, Undergraduate Study, TEI, Graduate Research Orientation, Standing Subcommittee on Engineering/Chemistry Liaison, Computer Affiliates Program, Search Committee for the Director of Budget and Resource Planning, CSL Computing and Networking, and CSRD Industrial Affiliates Program.

  • Chair, Architecture and Hardware Area, Department of Computer Science, 2004-2006.

  • Host to many speakers and visitors invited to the Department of Computer Science.

  • Participated and organized faculty retreats for the Computer Science Department, Computer Engineering, and College of Engineering.

  • Participated in several Illinois Computer Science Alumni Reunions across the nation.

Other Activities

  • Consultant for several companies.

  • Consultant for patent assessment. Member of the Round Table Group (RTG) Network of Patent Consultants.