CV OF JOSEP TORRELLAS (PDF VERSION here) Nov 2016.

Education

Experience

Honors and Awards

Main Professional Society Service

Designed Architectures

Distributed Software

Publications

Patents

Editorship of Journals

Recent Research Funding

Invited Lectures

Conference Organization. Steering Committee

Conference Organization. Chair

Conference Organization. Program Committee

Workshop Organization. Chair

Workshop Organization. Program Committee

Tutorials and Short Courses

Panels Organized

Participation in Panels

Talks at Workshops

Participation in Other Workshops and Meetings

Graduate Students

Postdoctoral Researchers and Visitors

Teaching Activity

Other Major Service Outside UIUC

Major Service Inside UIUC

Other Activities


Education

  • Ph.D. Electrical Engineering, Stanford University, 1992.
    Dissertation: "Multiprocessor Cache Memory Performance: Characterization and Optimization".
    Advisor: John Hennessy
  • M.S. Electrical and Computer Engineering, University of Wisconsin-Madison, 1987
  • B.S. Electrical Engineering, Universitat Politecnica de Catalunya, 1986

Experience

  • Saburo Muroga Professor of Computer Science, University of Illinois at Urbana-Champaign (UIUC), January 2016 - pres.
  • Director, Center for Programmable Extreme-Scale Computing, UIUC, January 2011 - pres.
  • Steering Committee Member, Illinois-Huawei Innovation Laboratory, UIUC, November 2016 - pres.
  • Director, Illinois-Intel Parallelism Center (I2PC), UIUC, September 2011 - September 2013
  • Professor, Computer Science Department, UIUC, August 2002 - pres.
  • Willett Faculty Scholar, Computer Science Dept., UIUC, August 2002 - August 2009
  • Leader, University of Illinois OpenSPARC Center of Excellence, UIUC, September 2007 - August 2010
  • Computer Architecture Leader, Universal Parallel Computing Research Center (UPCRC), UIUC, February 2008 - August 2011
  • Associate Professor, Computer Science Department, UIUC, August 1998 - August 2002
  • Research Staff Member, IBM T.J. Watson Research Center, IBM Research (sabbatical period), May 1998 - January 1999
  • Departmental Affiliate, Electrical and Computer Engineering Department, UIUC, April 1993 - pres.
  • Assistant Professor, Computer Science Department, UIUC, August 1992 - August 1998
  • Senior Computer Systems Engineer, Center for Supercomputing Research and Development (CSRD), UIUC, August 1992 - December 1996

Honors and Awards

  • 2017 University of Illinois at Urbana-Champaign Campus Award for Excellence in Graduate Student Mentoring.
  • 2016 Fellow of the American Association for the Advancement of Science (AAAS).
  • 2016 Member of the Board of Directors (Elected), Computing Research Association (CRA).
  • 2016 Saburo Muroga Professorship of Computer Science, UIUC.
  • 2015 IEEE Computer Society Technical Achievement Award, for "Pioneering contributions to shared-memory multiprocessor architectures and thread-level speculation".
  • 2015 Honorable Mention Paper, IEEE Micro Special Issue: 2015 Micro's Top Picks from Computer Architecture Conferences.
  • 2014 Distinguished Paper Award, International Conference on Programming Language Design and Implementation (PLDI), June 2014.
  • 2014 Best Paper Award Finalist, International Symposium on High Performance Computer Architecture (HPCA), February 2014.
  • 2013 Distinguished Speaker Award, IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP), June 2013.
  • 2012 High-Impact Paper Award, International Conference on Computer Design (ICCD), October 2012. For "One of the 5 most cited papers in the first 30 years of ICCD (1983-2012)".
  • 2012 Jon Postel Distinguished Lecturer, Computer Science Department, UCLA, November 2012.
  • 2010 ACM Fellow.
  • 2009 Best Paper Award, 42nd International Symposium on Microarchitecture (MICRO), December 2009.
  • 2009 Paper in IEEE Micro Special Issue: 2009 Micro's Top Picks from Computer Architecture Conferences.
  • 2009 Research Highlight paper in Communications of the ACM (CACM).
  • 2009 Best Idea Award, Wild and Crazy Ideas Session, at International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009.
  • 2007 Paper in IEEE Micro Special Issue: 2007 Micro's Top Picks from Computer Architecture Conferences.
  • 2006 Best Paper Award, 39th International Symposium on Microarchitecture (MICRO), December 2006.
  • 2006 Paper in IEEE Micro Special Issue: 2006 Micro's Top Picks from Computer Architecture Conferences.
  • 2004 Paper in IEEE Micro Special Issue: 2004 Micro's Top Picks from Computer Architecture Conferences.
  • 2004 IEEE Fellow.
  • 2003 Paper in IEEE Micro Special Issue: 2003 Micro's Top Picks from Computer Architecture Conferences.
  • 2002-2009 Willett Faculty Scholar, UIUC.
  • 2001 Best Paper Award, Fifth Workshop on Multithreaded Execution, Architecture, and Compilation.
  • 2000 Senior Xerox Award for Outstanding Faculty Research, UIUC.
  • 1997-00 IBM Partnership Award.
  • 1997 C. W. Gear Outstanding Junior Faculty Award, UIUC.
  • 1997 Junior Xerox Award for Outstanding Faculty Research, UIUC.
  • 1995,6,8 Intel Research Council Award.
  • 1994-9 National Science Foundation Young Investigator Award.
  • 1993-6 National Science Foundation Research Initiation Award.

Main Professional Society Service

  • Member, International Roadmap for Devices and Systems (IRDS) Applications Benchmarking Focus Team, September 2016 - pres.
  • Member, Board of Directors, Computing Research Association (CRA), July 2016 - pres.
  • Attendee, Leadership in Science Policy Institute Workshop, Computing Community Consortium (CCC), Washington DC, April 2015.
  • Council Member, The Computing Community Consortium (CCC), Computing Research Association (CRA). Member of the Subcommittee on Visioning Activities. January 2011 - June 2014.
  • Chair and co-editor, "SIGARCH/TCCA's Recommended Best Practices for ISCA Program Chairs", June 2013.
  • Co-editor, CCC Visioning white paper: "21st Century Computer Architecture, A Community White Paper", May 2012.
  • Member of the Executive Committee, The Institute of Electrical and Electronics Engineers (IEEE) Technical Committee on Computer Architecture (TCCA), October 2010 - 2019.
  • Chair, IEEE TCCA, July 2005 - October 2010. Main activities included:
    • Organize and fund about 10 technical conferences yearly.
    • Co-ordinate the funding and publicity of the Computer Architecture Letters.
    • Provide funds for students to travel to conferences.
    • Serve in the Steering Committee of conferences.
    • Successfully co-locate PPoPP and HPCA for interdisciplinary interactions.
  • Co-organizer of two CCC Visioning Workshops on Advancing Computer Architecture Research: "Failure is not an Option: Popular Parallel Programming" and "What Now in ILP Research?", both in 2010.
  • Participant in the CRA Visioning workshop: "Revitalizing Computer Architecture Research", December 2005.
  • Vice-Chair and Member of the Advisory Board, IEEE TCCA, 1998 - July 2005.

Designed Architectures

Distributed Software

Publications

Patents

  • "Exploiting Spatial Locality to Reduce Refresh Energy in On-Chip eDRAM Modules",
    by Aditya B. Agrawal, Amin Ansari, and Josep Torrellas, 2013.
  • "Exposing Control of Power and Clock Gating for Software",
    by Nicholas P. Carter, Joshua B. Fryman, Robert C. Knauerhase, Aditya B. Agrawal, and Josep Torrellas, 2012.
  • "Architecture Support System and Method for Memory Monitoring",
    by Yuanyuan Zhou, Josep Torrellas, and Pin Zhou, US patent number 7,711,988, May 2010.

Editorship of Journals

  • Board of Distinguished Reviewers for the ACM TACO journal, 2013 - 2014.
  • Associate Editor, ACM Transactions on Architecture and Code Optimization (TACO), March 2003 - January 2006.
  • Member of the Editorial Board, IEEE Computer Architecture Letters (CAL), December 2001 - January 2006.

Recent Research Funding

  • Nov 2016, $260 K, SK Hynix, lead PI: J. Torrellas, num PIs: 1. Title: Page Management in Hybrid DRAM-NVM Memory Systems.
  • Aug 2016, $880 K, NSF XPS, lead PI: J. Torrellas, num PIs: 3. Title: XPS:FULL:Breaking the Scalability Wall of Shared Memory through Fast On-Chip Wireless Communication.
  • Aug 2016, $300 K, NSF CCF, lead PI: J. Torrellas, num PIs: 1. Title: Eager: Technologies for Ultra Energy-Efficient Multicores.
  • Aug 2015, $500 K, NSF CCF, lead PI: J. Torrellas, num PIs: 1. Title: Architectures for Scripting Languages.
  • Sep 2012, $2.8 M ($1.77M received), DARPA PERFECT, lead PI: J. Torrellas, num PIs: 3. Title: Parameter Variation at NT Voltage: The Power Efficiency versus Resilience Tradeoff.
  • Sep 2012, $8.4 M DOE X-Stack + $3.6M cost share, lead PI: S. Borkar, num PIs: 8. Title: Traleika Glacier X-Stack.
  • Sep 2012, $100 K, Mr. Bruce Ge Fund, lead PI: J. Torrellas, num PIs: 1. Title: Improving Computer Systems.
  • Sep 2011, $2 M Intel, plus $1.6M from the University of Illinois, lead PI: J. Torrellas, num PIs: 6. Title: Illinois-Intel Parallelism Center (I2PC).
  • Jul 2011, $430 K, NSF CSR, lead PI: J. Torrellas, num PIs: 1. Title: Framework for Concurrency Debugging.
  • Sep 2010, $2.4 M, NSF CCF, lead PI: J. Torrellas, num PIs: 4. Title: Programmable Many-Core for Extreme Scale Computing.
  • Jul 2010, $25.8M DARPA UHPC, plus $23.2M from Intel, lead PI: S. Borkar, num PIs: 14. Title: Runnemede: An Architecture for Ubiquitous High Performance Computing.
  • Aug 2010, $1.9 M, DOE ASCR, lead PI: J. Torrellas, num PIs: 4. Title: Thrifty: An Exascale Architecture for Energy Proportional Computing.
  • May 2010, $70 K, NSF CSR, lead PI: S. King, num PIs: 2. Title: Supplemental on Deterministic Multiprocessor Replay.
  • Aug 2009, $23 K, DARPA TCTO, lead PI: J. Torrellas, num PIs: 1. Title: Study on Extreme Scale Multiprocessors.
  • Jun 2009, $168 K, NSF CPA, lead PI: J. Torrellas, num PIs: 3. Title: Supplemental on Addressing the Parameter Variation Challenge.
  • Feb 2009, $90 K cash + $30 K equipment, Sun Microsystems, lead PI: J. Torrellas, num PIs: 9. Title: UIUC OpenSPARC Center of Excellence.
  • Sep 2008, $350 K, NSF CSR, lead PI: S. King, num PIs: 2. Title: Recording and Deterministically Replaying Shared-memory Multiprocessors.
  • Mar 2008, $120 K cash + $50 K equipment, Sun Microsystems, lead PI: J. Torrellas, num PIs: 9. Title: UIUC OpenSPARC Center of Excellence.
  • Feb 2008, $6M Intel and Microsoft, plus $4.8M from the University of Illinois, lead PI: M. Snir and W. Hwu, num PIs: 15. Title: Universal Parallel Computing Research Center.
  • Sep 2007, $890 K, NSF CSR, lead PI: J. Torrellas, num PIs: 5. Title: Novel Programming Models and Architectures to Simplify Parallel Programming.
  • Jul 2007, $1,200 K, NSF CPA, lead PI: J. Torrellas, num PIs: 3. Title: Addressing the Parameter-Variation Challenge through a Cross-Disciplinary Architecture, CAD, and Compiler Approach.
  • Apr 2007, $360 K, Semiconductor Research Corporation, lead PI: J. Torrellas, num PIs: 2. Title: Timing Faults Due to Parameter Variation.
  • Nov 2004, $40 K cash + 25 K equipment, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Speculative Multithreading.
  • Nov 2004, $500 K, DOE Extreme Scale Computation, lead PI: J. Nieplocha, num PIs: 6. Title: Scalable Fault Tolerant Runtime and OS.
  • Sep 2003, $1,000 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 4. Title: Automatic Detection and Correction of Bugs.
  • Jul 2003, $3,000 K, DARPA-IPTO/IBM/UIUC, lead PI: J. Torrellas, num PIs: 4. Title: IBM PERCS High-Productivity Computer System.
  • Apr 2003, $14 K, UIUC-CNRS, lead PI: D. Padua, num PIs: 6. Title: Program Optimization.
  • Jul 2002, $100 K, DARPA-IPTO/IBM, lead PI: J. Torrellas, num PIs: 3. Title: IBM PERCS High-Productivity Computer System.
  • Sep 2002, $500 K, DOD, lead PI: M. Snir, num PIs: 2. Title: Superconducting Switch for Teraflop Architecture.
  • Sep 2001, $1,375 K, NSF Medium ITR, lead PI: J. Torrellas, num PIs: 2. Title: Novel Scalable Simulation.
  • Aug 2001, $750 K, NSF-NGS, lead PI: D. Padua, num PIs: 3. Title: Open MP for Networked Computing.
  • Aug 2001, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
  • Jun 2001, $2,700 K, DARPA-IPTO, lead PI: J. Torrellas, num PIs: 6. Title: Morphable Multithreaded Memory Tiles.
  • Sep 2000, $1,900 K, NSF-EIA, lead PI: J. Torrellas, num PIs: 3. Title: FlexRAM: Intelligent Memory Architecture.
  • Sep 2000, $500 K, NSF-ITR, lead PI: J. Torrellas, num PIs: 4. Title: Solving the Protein Folding Problem.
  • Dec 2000, $750 K, IBM, lead PI: D. Reed, num PIs: 4. Donation of a 16-node SP2 machine.
  • Aug 1999, $10 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. HPCA travel grant.
  • Sep 1999, $300 K, NSF-NGS, lead PI: L. Rauchwerger, num PIs: 3. Title: Application Centric Computing.
  • Jun 1999, $325 K, NSF-CCR, lead PI: J. Torrellas, num PIs: 1. Title: New Architectures to Run Commercial Workloads.
  • Sep 1999, $15 K, IBM, lead PI: J. Torrellas, num PIs: 1. Joint study.
  • Feb 1998, $75 K in cash and $60 K in equip, Intel, lead PI: J. Torrellas, num PIs: 1. Title: Evaluating Database Workloads on Multiprocessors.
  • Aug 1997, $25 K, Commission Scientific Exchange USA-Spain, lead PI: J. Larriba, num PIs: 3. Title: Multiprocessor Computer Architectures and Databases.
  • Jun 1997, $110 K, IBM, lead PI: J. Torrellas, num PIs: 1. IBM Partnership.
  • Jun 1997, $455 K, NSF-MIPS, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
  • Jun 1996, $100 K, NSF-ASC, lead PI: J. Torrellas, num PIs: 2. Title: Illinois Aggressive COMA Multiprocessor.
  • Sep 1995, $1,213K, DARPA-ITO, lead PI: D. Padua, num PIs: 3. Title: Polaris: A Parallelizing Compiler.

Invited Lectures

  • "Toward Extreme-Scale Manycore Architectures".
    • Keynote, at International Conference on High Performance Computing, Data, and Analytics (HiPC), Hyderabad, India, December 2016.
    • At University of Southern California, CA, October 2016.
    • At University of Texas, Austin, TX, September 2016.
    • At SUNY Binghamton, Binghamton, NY, September 2016.
    • At Seoul National University, Korea, June 2016.
    • Keynote, at International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
    • Keynote, at Workshop on Big Data Benchmarks, Performance Optimization, and Emerging Hardware (BPOE), April 2016 .
  • "WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication".
    • At ARM Research Summit, September 2016.
    • At Intel, Extreme Scale Tech. Rev. Mtg, September 2016.
  • "CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization".
    • At Intel, Extreme Scale Tech. Rev. Mtg, May 2016.
  • "ScalCore: Designing a Core for Voltage Scalability".
    • At Intel, Extreme Scale Tech. Rev. Mtg, March 2016.
  • "Improving JavaScript Performance".
    • At Intel Laboratories, Santa Clara, CA, April 2014.
  • "Toward Programmable High-Performance Multicores".
    • At University of Washington, Seattle, WA, January 2015.
    • At Stanford University, Stanford, CA, May 2014.
    • At Qualcomm Research, San Jose, CA, December 2013.
    • At University of Cyprus, Nicosia, Cyprus, July 2013.
    • At Technion, Haifa, Israel, June 2013.
    • At Intel Haifa, Israel, June 2013.
    • At Princeton University, April 2013.
    • At Harvard University, April 2013.
    • At Massachussets Institute of Technology, April 2013.
    • At University of California Berkeley, April 2013.
    • At Intel Laboratories, Santa Clara, CA, April 2013.
    • At Carnegie-Mellon University, April 2013.
  • "Boosting the Energy Efficiency of Low-Voltage Multicores".
    • At Qualcomm, San Diego, CA, August 2014.
    • At Qualcomm, Raleigh, NC, February 2014.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, January 2014.
    • At AMD, Austin, TX, December 2013.
    • At Intel, Hillsboro, OR, December 2013.
  • "Tackling Parameter Variation from an Architectural Perspective".
    • Keynote, at International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, October 2014.
  • "Extreme Scale Computer Architecture: Energy Efficiency from the Ground Up".
    • Keynote, at Workshop on Architectures and Systems for Big Data (ASBD), June 2014.
    • At Office of Technology Management, University of Illinois, October 2013.
    • Keynote, IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), George Washington University Virginia Science and Technology Campus, VA, June 2013.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, February 2013.
    • Invited Speaker, Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH), Shenzhen, China, February 2013.
    • At Shanghai Jiao Tong University, Shanghai, February 2013.
    • At National University of Defense Technology (NUDT), Changsha, China, February 2013.
    • At Institute for Computing Technology, Chinese Academy of Sciences, Beijing, December 2012.
    • At Beihang University, Beijing, December 2012.
    • At Tsinghua University, Beijing, December 2012.
    • At Pekin University, Beijing, December 2012.
    • Keynote, Workshop on Near-Threshold Computing (NTC), Vancouver, Canada, December 2012.
    • Jon Postel Distinguished Lecture, Computer Science Department, UCLA, November 2012.
  • "Vulcan: Hardware Support for Detecting Sequential Consistency Violations in Programs Dynamically".
    • At I2PC Distinguished Speaker Series, University of Illinois, September 2012.
  • "Low Power Architectural Trends".
    • At Nortwestern University, October 2011.
  • "Novel Techniques to Debug Multithreaded Programs".
    • At Microsoft Research Asia, Beijing, December 2012.
    • At Intel Programming Systems Laboratory, October 2010.
  • "The Bulk Multicore Architecture for Programmability".
    • At Seoul National University, Seoul, Korea, September 2011.
    • At Samsung Advanced Institute of Technology, Seoul, Korea, September 2011.
    • At KAIST, Daejeon, Korea, September 2011.
    • At Samsung System LSI division, Seoul, Korea, September 2011.
    • At Pohang University of Science and Technology, Pohang, Korea, September 2011.
    • At University of Florida, Gainesville, FL, February 2011.
    • At University of Michigan, Ann Arbor, MI, April 2010.
    • Keynote, at 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects, Bangalore, India, January 2010.
    • At Intel, Bangalore, India, January 2010.
    • At DARPA-IPTO, Washington, DC, October 2008.
    • At Stanford University, Stanford, CA, October 2008.
    • At Intel Laboratories, Hillsboro, OR, October 2008.
    • At Sun Microsystems, Santa Clara, CA, October 2008.
    • At UIUC-UPCRC Research Seminar, Urbana, IL, October 2008.
    • At Microsoft Research, Redmond, WA, September 2008.
    • At Intel Laboratories, Santa Clara, CA, August 2008.
    • At Institute for Computing Technology, Chinese Academy of Sciences, Beijing, June 2008.
    • At Tsinghua University, Beijing, June 2008.
    • At Beijing University of Aeronautics and Astronautics, Beijing, June 2008.
    • At Microsoft Research, Beijing, June 2008.
    • At IBM Research, Beijing, June 2008.
    • At Intel Laboratories, Barcelona, June 2008.
    • At Carnegie Mellon University, June 2008.
    • At University of California Berkeley, May 2008.
    • At Massachussets Institute of Technology, May 2008.
    • At Harvard University, May 2008.
    • At IBM T.J. Watson Research Center, Yorktown, NY, May 2008.
    • At Texas A&M University, April 2008.
    • At Georgia Institute of Technology, April 2008.
    • At University of Texas at Austin, April 2008.
    • At University of Tokyo, April 2008.
    • At Rice University, April 2008.
  • "Parameter Variation-Tolerant Computer Architectures".
    • Distinguished Speaker Colloquium, ECE Department, North Carolina State University, Raleigh, NC, March 2012.
    • At IBM Research, Austin, TX, February 2011.
    • At University of Minnesota, Minneapolis, MN, December 2010.
    • At Intel, Marlborough, MA, January 2009.
    • Keynote, at Los Alamos Computer Science Symposium (LACSS), Santa Fe, October 2008.
    • At Department of Computer Science Distinguished Lectures, UIUC, Urbana, IL, October 2008.
    • Keynote, at Workshop on Quality-Aware Design, June 2008.
    • At Intel Microarchitecture Research Laboratory, Hillsboro, OR, March 2008.
    • Invited Talk at IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips X), Yokohama, Japan, April 2007.
    • At Waseda University, Tokyo, April 2007.
    • Invited Talk at Third IBM TJ Watson Conference on Interaction between Architecture, Circuits and Compilers (PAC2), October 2006.
    • At Department of Electrical and Computer Engineering, University of Toronto, December 2005.
    • At VLSI Circuits Seminar, Department of Electrical and Computer Engineering, University of Illinois at Urbana Champaign, October 2005.
  • "An Agenda for Parallel Computer Architecture and Parallel Computing".
    • At Texas A&M University, April 2009.
  • "Practical Deterministic Multiprocessor Replay".
    • At Intel Laboratories, Santa Clara, CA, December 2009.
    • At Microsoft, Redmond, WA, April 2009.
    • At Intel, Hillsboro, OR, April 2009.
  • "Designing Multicores for Single-Thread Performance".
    • At IBM T.J. Watson Research Center, Yorktown, NY, February 2009.
    • At Sun Microsystems, Santa Clara, CA, December 2008.
  • "Speculative Multithreading Architectures".
    • At Intel Microarchitecture Research Laboratory, Hillsboro, OR, August 2006.
  • "A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads".
    • At IBM PERCS Virtual Seminar, January 2005.
  • "Hardware-Supported Data Race Detection".
    • At Intel, Champaign, IL, April 2005.
    • At Intel, Champaign, IL, November 2004.
  • "Using Thread Level Speculation for Performance and to Enhance Software Debugging and Programmability".
    • At Cornell University, Ithaca, NY, November 2004.
    • At SUN Microsystems, Sunnyvale, CA, August 2004.
    • At Intel, Champaign IL, January 2004.
    • At Universidad Complutense de Madrid, Spain, June 2003.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, April 2003.
    • At Intel Microprocessor Research Laboratory, Santa Clara CA, March 2003.
  • "Challenging Issues in Speculative Multithreading".
    • At Carnegie-Mellon University, Pittsburgh PA, December 2002.
    • At University of Rochester, Rochester NY, December 2002.
    • At Intel, Marlboro, MA, May 2002.
    • At Compaq Computer, Shrewsbury, MA, May 2002.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, July 2000.
  • "FlexRAM: Toward an Advanced Intelligent Memory System".
    • At Los Alamos National Laboratory, Los Alamos NM, September 2002.
    • At Purdue University, West Lafayette, IN, April 2002.
    • At Intel, Champaign IL, December 2001.
    • Keynote Speech at XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
    • At Los Alamos National Laboratory, Los Alamos NM, March 2001.
    • At Massachusetts Institute of Technology (MIT), February 2001.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, October 2000.
    • At Universidad Politecnica de Madrid, Spain, January 2000.
    • At Chalmers University, Gothenburg, Sweden, December 1999.
    • At Intel Corporation, Hillsboro, OR, November 1999.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, August 1999.
    • At Univeriste de Versailles, France, July 1999.
    • At DARPA ITO Data Intensive Systems PI Meeting, Del Mar, CA, February 1998.
  • "New Research Topics in Computer Architecture".
    • At Universidad de Zaragoza, Zaragoza, Spain, June 2002.
  • "A Framework for Dynamic Energy Efficiency and Temperature Management".
    • At Universitat Politecnica de Catalunya, Barcelona, December 2000.
  • "Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability".
    • At Institute for Scientific Computing, Aachen, Germany, August 1999.
  • "Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors".
    • At Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
    • At National Center for Supercomputing Applications (NCSA), Urbana, IL May 1999.
  • "New Trends in Computer Architecture and the i-acoma Scalable Multiprocessor Project".
    • At NEC Corporation, Fuchu City, Japan, September 1999.
    • At Waseda University, Tokyo, Japan, September 1999.
    • At University of Houston, Houston, TX, January 1999.
    • At Universidade de A Corunha, A Coruhna, Spain, December 1998.
    • At Universidade de Santiago, Santiago, Spain, December 1998.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1998.
    • At New York University, NY, October 1998.
    • At DARPA, Washington, DC, September 1998.
    • At NSF, Washington, DC, September 1998.
    • At the National Center for Supercomputing Applications, Urbana, IL, May 1998.
    • At Intel Corporation, Hillsboro, OR, April 1998.
    • At VLSI Circuits Seminar, University of Illinois at Urbana Champaign, April 1998.
  • "Efficient Execution of Database Workloads under Deep Memory Hierarchies".
    • At Pennsylvania State University, State College, PA, November 1998.
    • At Oracle Corporation, Redwood Shores, CA, February 1998.
    • At Hewlett Packard Laboratories, Palo Alto, CA, February 1998.
  • "New Results in the Illinois Aggressive COMA Multiprocessor Project".
    • At Los Alamos National Laboratory, Los Alamos NM, May 1998.
    • At Hewlett Packard Laboratories, Palo Alto, CA, February 1998.
    • At Texas A\&M University, College Station, TX, January 1998.
    • At Convex Computer, Dallas, TX, January 1998.
    • At Northwestern University, Evanston, IL, December 1997.
    • At University of Washington, Seattle, WA, October 1997.
    • At Carnegie-Mellon University, Pittsburgh, PA, October 1997.
    • At Sequent Computers, Hillsboro, OR, April 1997.
    • At Silicon Graphics, Mountain View, CA, January 1997.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, November 1996.
  • "Exploiting Billion-Transistor Chips for Multiprocessing".
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, December 1997.
    • At Reflections/Projections ACM Student Chapter Conference, Urbana, IL, October 1997.
  • "The Illinois Aggressive COMA Multiprocessor".
    • At Department of Computer Science, Tsinghua University, Beijing, China, January 1997.
    • At University of California-Berkeley, Berkeley, CA, February 1996.
    • At Stanford University, Stanford, CA, February 1996.
    • At Tandem Computers, Cupertino, CA, August 1995.
    • At SUN Microsystems, Mountain View, CA, August 1995.
    • At Universidad Politecnica de Valencia, Valencia, Spain, June 1995.
    • At Universite Paul Sabatier, Toulouse, France, June 1995.
    • At Intel Scalable Systems Division, Intel Corporation, Beaverton, OR, May 1995.
    • At IBM T.J. Watson Research Center, Yorktown Heights, NY, February 1995.
    • At Digital Equipment Corporation, Hudson, MA, February 1995.
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1994.
  • "The Performance of the Cedar Multistage Interconnection Network".
    • At Universitat Politecnica de Catalunya, Barcelona, Spain, December 1993.

Conference Organization. Steering Committee

  • Jul 2005 - pres., IEEE/ACM International Symposium on Computer Architecture (ISCA).
  • Jul 2005 - pres., IEEE International Symposium on High-Performance Computer Architecture (HPCA).
  • Apr 2006 - Feb 2008, ACM Symposium on Principles and Practice of Parallel Programming (PPoPP).
  • Sep 2005 - Oct 2007, Aug 2014 - pres., IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT).

Conference Organization. Chair

  • Program Chair. The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT), Edmonton, Canada, August 2014.
  • Program Chair. The 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
  • Vice-General Chair. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), Yokohama, Japan, 2008-2016.
  • General Co-Chair. International Conference on Network and Parallel Computing (NPC), Shanghai, China, October 2008.
  • Technical Papers Co-Chair. IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC07), Reno, NV, November 2007.
  • General Chair. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New York, NY, March 2006.
  • Program Chair. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
  • General Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Saint Louis, MO, September 2005.
  • Program Chair. The 11th International Symposium on High-Performance Computer Architecture (HPCA), San Francisco, CA, February 2005.
  • Architecture Area Chair. International Conference for High Performance Computing Networks and Storage (SC03), Phoenix, AZ, November 2003.
  • Program Vice-Chair for Architecture. The 17th International Parallel and Distributed Processing Symposium (IPDPS), Nice, France, April 2003.
  • Vice-Chair of Architecture. The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.
  • General Co-Chair. The 6th International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.
  • Minitrack Organizer. Minitrack on Scalable Shared-Memory Architectures. The 28th Hawaii International Conference on System Sciences (HICSS), Hawaii, January 1995.

Conference Organization. Program Committee & Other

  • Program Committee Member. International Symposium on Computer Architecture (ISCA), Toronto, Canada, June 2017.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xian, China, April 2017.
  • Program Committee Member. International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, February 2017.
  • External Program Committee Member. International Symposium on Microarchitecture (MICRO), Taipei, Taiwan, October 2016.
  • Program Committee Member. International Conference on Parallel Architectures and Compilation Techniques (PACT), Haifa, Israel, September 2016.
  • External Program Committee Member. International Symposium on Computer Architecture (ISCA), Seoul, Korea, June 2016.
  • External Program Committee Member. International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, March 2016.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, April 2016.
  • External Program Committee Member. International Symposium on Microarchitecture (MICRO), Waikiki, HI, December 2015.
  • External Program Committee Member. International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015.
  • Program Committee Member. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, May-June 2015.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Istanbul, Turkey, March 2015.
  • Program Committee Member. The 21st International Symposium on High-Performance Computer Architecture (HPCA), San Francisco, CA, February 2015.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Salt Lake City, UT, March 2014.
  • Program Committee Member. The 40th International Symposium on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013.
  • Program Committee Member. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, May-June 2013.
  • External Program Committee Member. International Symposium on Microarchitecture (MICRO), Vancouver, Canada, December 2012.
  • Program Committee Member. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, May-June 2012.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), London, UK, March 2012.
  • Program Committee Member. The 18th International Symposium on High-Performance Computer Architecture (HPCA), New Orleans, LA, February 2012.
  • Program Committee Member. International Conference on Parallel Architectures and Compilation Techniques (PACT), Galveston Island, TX, October 2011.
  • Program Committee Member. The 38th International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Newport Beach, CA, March 2011.
  • Program Committee Member. The 17th International Symposium on High-Performance Computer Architecture (HPCA), San Antonio, TX, February 2011.
  • Technical Papers Committee Member. International Conference for High Performance Computing Networks and Storage} (SC), November 2010.
  • Program Committee Member. The 37th International Symposium on Computer Architecture (ISCA), Saint Malo, France, June 2010.
  • External Program Committee Member. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Pittsburgh, PA, March 2010.
  • Program Committee Member. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2010.
  • Program Committee Member. The 16th International Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, January 2010.
  • Program Committee Member. The 36th International Symposium on Computer Architecture (ISCA), Austin, TX, June 2009.
  • Program Committee Member. The 15th International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, NC, February 2009.
  • Program Committee Member. Architecture Track. IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), Austin, TX, November 2008.
  • Program Committee Member. The 35th International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
  • Program Committee Member. The 14th International Symposium on High-Performance Computer Architecture (HPCA), Salt Lake City, UT, February 2008.
  • Program Committee Member. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, January-February 2008.
  • Program Committee Member. International Conference on High Performance Embedded Architectures and Compilers (HIPEAC), Goteborg, Sweden, January 2008.
  • Program Committee Member. The 34th International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2007.
  • Program Committee Member. The 33rd International Symposium on Computer Architecture (ISCA), Boston, MA, June 2006.
  • Program Committee Member. The 12th International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, February 2006.
  • Technical Papers Committee Member. International Conference for High Performance Computing Networks and Storage (SC05), Seattle, WA, November 2005.
  • Program Committee Member. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Chicago, IL, June 2005.
  • Program Committee Member. Industrial Perspectives on Challenges for Next-Generation Computer Systems, The 11th International Symposium on High-Performance Computer Architecture, (HPCA), San Francisco, CA, February 2005.
  • Program Committee Member. The 37th Annual International Symposium on Microarchitecture (MICRO), Portland, OR, December 2004.
  • Publications Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Antibes, France, September 2004.
  • Program Committee Member. The 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, June 2004.
  • Program Committee Member. The 10th International Symposium on High-Performance Computer Architecture (HPCA), Madrid, February 2004.
  • Program Committee Member. The 36th Annual International Symposium on Microarchitecture (MICRO), San Diego, December 2003.
  • Program Committee Member. The 17th ACM International Conference on Supercomputing (ICS), San Francisco, June 2003.
  • Program Committee Member. The 9th International Symposium on High-Performance Computer Architecture (HPCA), Anaheim, CA, February 2003.
  • Technical Papers Committee Member. International Conference for High Performance Computing Networks and Storage (SC02), Baltimore, MD, November 2002.
  • Program Committee Member. The 8th International Symposium on High-Performance Computer Architecture (HPCA), Boston, February 2002.
  • Program Committee Member. The 16th International Parallel and Distributed Processing Symposium (IPDPS), Fort Lauderdale, FL, April 2002.
  • Finance Chair. International Conference on Parallel Architectures and Compilation Techniques (PACT), Barcelona, September 2001.
  • Program Committee Member. The 28th Annual International Symposium on Computer Architecture (ISCA), Goteborg, Sweden, June 2001.
  • Tutorials Chair. The 28th Annual International Symposium on Computer Architecture (ISCA), Goteborg, Sweden, June 2001.
  • Program Committee Member. 15th International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, April 2001.
  • Program Committee Member. The 7th International Symposium on High-Performance Computer Architecture (HPCA), Monterrey, Mexico, January 2001.
  • Publicity Chair. International Conference on High Performance Computing (HIPC), India, December 2000.
  • Program Committee Member. International Conference on Parallel Architectures and Compilation Techniques (PACT), Philadelphia, October 2000.
  • Program Committee Member. The 2000 International Conference on Parallel Processing (ICPP), Toronto, Canada, August 2000.
  • Program Committee Member. The International Conference on High Performance Computing (HIPC99), India, December 1999.
  • Program Committee Member. The 13th ACM International Conference on Supercomputing (ICS), Rhodes, Greece, June 1999.
  • Program Committee Member. The 1999 International Conference on Parallel Processing (ICPP), Aizu-Wakamatsu, Fukushima, Japan, September 1999.
  • Program Committee Member. The 7th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'99), Annapolis, Maryland, February 1999.
  • Program Committee Member. The 5th International Symposium on High-Performance Computer Architecture (HPCA), Orlando, FL, January 1999.
  • Program Committee Member. The 1998 International Conference on Parallel Processing (ICPP), Minneapolis, MN, August 1998.
  • Workshops Chair. The 25st Annual International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
  • Program Committee Member. The 1998 ACM Sigmetrics Conference, Madison WI, June 1998.
  • Program Committee Member. The 1998 International Parallel Processing Symposium (IPPS), Orlando FL, March 1998.
  • Workshops and Tutorials Chair. 4th International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, February 1998.
  • Program Committee Member. The 4th International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, February 1998.
  • Program Committee Member. The 1997 International Conference on Parallel Processing (ICPP), Chicago, IL, August 1997.
  • Program Committee Member. The 11th ACM International Conference on Supercomputing (ICS), Vienna, Austria, July 1997.
  • Program Committee Member. The 6th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'96), Annapolis, Maryland, October 1996.
  • Program Committee Member. The 10th ACM International Conference on Supercomputing (ICS), Philadelphia, Pennsylvania, May 1996.
  • Registration Chair. 2nd International Computer Performance and Dependability Symposium (ICPDS), Urbana IL, September 1996.
  • Program Committee Member. The 15th International Conference of the Chilean Computer Science Society (ICCCSS), Arica, Chile, November 1995.
  • Program Committee Member. The 15th International Conference on Distributed Computing Systems (ICDCS), Vancouver, Canada, May 1995.
  • Program Committee Member. 1st International Computer Performance and Dependability Symposium (ICPDS), Erlangen, Germany, April 1995.
  • Program Committee Member. The 14th International Conference on Distributed Computing Systems (ICDCS), Poznan, Poland, June 1994.
  • Registration Chair. The 21st Annual International Symposium on Computer Architecture (ISCA), Chicago, IL, April 1994.

Workshop Organization. Chair

Workshop Organization. Program Committee & Other

  • Program Committee Member. Workshop on Near-Threshold Computing (WNTC), Minneapolis, MN, June 2014.
  • Program Committee Member. Workshop on Determinism and Correctness in Parallel Programming (WODET), Houston, TX, March 2013.
  • Program Committee Member. Workshop on Near-Threshold Computing (WNTC), Vancouver, Canada, December 2012.
  • Program Committee Member. Workshop on Hardware Support for Parallel Program Correctness, Porto Alegre, Brazil, December 2011.
  • Program Committee Member. The 3rd Workshop on System Effects of Logic Soft Errors (SELSE-III), Austin, TX, April 2007.
  • Program Committee Member. The 1st Workshop on Multithreaded Architectures and Applications (MTAAP), Long Beach, CA, March 2007.
  • Program Committee Member. The 2nd Workshop on System Effects of Logic Soft Errors (SELSE-II), Urbana-Champaign, IL, April 2006.
  • Program Committee Member. The 3rd Workshop on Power-Aware Computer Systems (PACS), San Diego, December 2003.
  • Program Committee Member. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Istambul, Turkey, November 2002.
  • Program Committee Member. 5th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Austin, December 2001.
  • Program Committee Member. 4th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Monterey, December 2000.
  • Program Committee Member. The 2nd Workshop on Intelligent Memory Systems, Boston, November 2000.
  • Program Committee Member. 3rd Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Toulouse, France, January 2000.
  • Program Committee Member. 2nd Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), Orlando, FL, January 1999.

Tutorials and Short Courses

  • Course on "Modern Shared-Memory Parallel Computer Architecture", at Beihang University, Beijing, China, December 2012. 12 hours.
  • "High Performance Computing Architectures -- Trends and Directions", at UIUC Course on High Performance Computing, Singapore, June 2010.
  • "Parallel@Illinois Symposium at Singapore", Singapore, June 2010.
  • Course on "Multiprocessor Architectures for Speculative Multithreading", at Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), L'Aquila, Italy, July 2008.
  • Short course on "Boosting Machine Performance with Thread-Level Speculation", at Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.
  • Short course on "New Technologies in Computer Architecture", at Universidad de Zaragoza, Spain, June 2002.
  • Tutorial on "Performance Modeling Using Hardware Counters", at International Symposium on High-Performance Computer Architecture (HPCA), Toulouse, France, January 2000.
  • Short course on "Scalable Shared-Memory Multiprocessors", at Universitat Politecnica de Catalunya, Barcelona, Spain, July 1998.
  • Tutorial on "Scalable Shared-Memory Multiprocessors: Architecture and Implementation Issues", at VII Jornadas de Paralelismo, Santiago, Spain, September 1996.

Panels Organized

  • "Broadening Computer Architecture Research: Embracing New Areas to Keep the Field Vibrant", International Symposium on Computer Architecture, San Jose, CA, June 2011.
  • "Extreme Scale Computing: Challenges and Opportunities", International Symposium on High-Performance Computer Architecture and International Conference on Principles and Practice of Parallel Programming, Bangalore, India, January 2010.
  • "High-Performance Architecture Research", Indo-US Workshop on Parallelism and the Future of High-Performance Computing, Bangalore, India, January 2010.
  • Minipanel on "Speculative Multithreading Architectures", International Symposium on Computer Architecture, Austin, TX, June 2009.
  • "How to Build a Useful Thousand-Core Manycore System?", IEEE International Parallel and Distributed Processing Symposium (IPDPS), Rome, Italy, May 2009.
  • "Multi-Core and Many-Core: the 5 to 10 Year View", IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, April 2009.
  • "Wish List: Architectural Support and Tool Infrastructure for Improving Software Dependability", Workshop on Architectural and System Support for Improving Software Dependability (ASID), in conjunction with ASPLOS-XII, San Jose, CA, October 2006.
  • "An Agenda for Computer Architecture Research on Hardware Complexity", Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA-33, Boston, MA, June 2006.
  • "Soft Error Rate (SER) Scaling Trends", Workshop on System Effects of Logic Soft Errors (SELSE), Urbana-Champaign, IL, April 2006.
  • "New Technologies in Computer Architecture", Dagstuhl Seminar on Performance Analysis and Distributed Computing (PADC), Dagstuhl, Germany, August 2002.
  • "What's the Most Critical Challenge is Supporting Multimedia Applications", The 2001 International Conference on Parallel Processing (ICPP), Valencia, Spain, September 2001.
  • "Designing Scalable Shared-Memory Multiprocessors Using Commodity Microprocessors and OS: NUMA vs COMA Implementation", Fifth Workshop on Scalable Shared-Memory Multiprocessors, Santa Margherita, Italy, June 1995.

Participation in Panels

  • "Architecture and System for Big Data Processing", Workshop on Architectures and Systems for Big Data (ASBD), Minneapolis, MN, June 2014.
  • "Future Applications and Challenges for NTC", Workshop on Near-threshold Computing, Minneapolis, MN, June 2014.
  • "The Future of Parallelism", 2013 Illinois Symposium on Parallelism: Current State of the Field and the Future, Urbana, IL, September 2013.
  • "Research Directions for 21st Century Computer Systems", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Houston, TX, March 2013.
  • "Future of Computing Systems", IBM T.J. Watson Research Center, Yorktown Heights, NY, February 2013.
  • "Is Reliability the Main Roadblock to Ultra-Low Voltage Operation?", Workshop on Near-threshold Computing (WNTC), Vancouver, Canada, December 2012.
  • "Many Core -- Does It Work?", 8th Workshop on Duplicating, Deconstructing, and Debunking (WDDD), Austin, TX, June 2009.
  • "How to Place Students in Top-5 Departments", Department of Computer Science, UIUC, April 2009.
  • "Silicon Errors in Modern Integrated Circuits: What are the Main Threats", Third Workshop on System Effects of Logic Soft Errors (SELSE-III), Austin, IL, April 2007.
  • "Chip Design in the Nano Era", International Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2005.
  • "What Are the Important Research Challenges in Temperature-Aware Computer Systems?", Second Workshop on Temperature-Aware Computer Systems, Madison, WI, June 2005.
  • "Current and Future Processors", Cursos de Verano, Universidad Complutense de Madrid, El Escorial, Spain, July 2004.
  • "Research Challenges for the Architecture Community in Temperature-Aware Design", First Workshop on Temperature-Aware Computer Systems, Munich, Germany, June 2004.
  • "New Architectural Technologies", DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "What does the Future Hold for Parallel Languages?", The 16th International Workshop on Languages and Compilers for Parallel Computing, College Station, TX, October 2003.
  • "Future Architectures and Programming Models for High Performance Computing", International Symposium on Principles and Practice of Parallel Programming (PPoPP), San Diego, June 2003.
  • "Research in Computer Architecture", XII Jornadas Nacionales de Paralelismo, Valencia, Spain, September 2001.
  • "Microprocessor Design Beyond the PC Era: Is There Room for Innovation?", 15th International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, April 2001.
  • "What Tools Do We Use to Evaluate Future Memory Systems?", Third Workshop on Computer Architecture Evaluation Using Commercial Workloads, Toulouse, France, January 2000.
  • "Findings of the Petaflop Workshops", The 7th IEEE Symposium on the Frontiers of Massively Parallel Processing (Frontiers'99), Annapolis, MD, February 1999.
  • "Issues in Petaflop Machines", The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
  • "Cooperation Between Industry, Academia and Government to Make Commercial Applications Widely Available", Second Workshop on Computer Architecture Evaluation Using Commercial Workloads, Orlando, FL, January 1999.
  • "Microbenchmarks: Risk versus Utility", Workshop on Performance Analysis and its Impact on Design (PAID), Barcelona, June 1998.
  • "The First Course: Bottom-Up or Top-Down? Which is More Effective?", Fourth Workshop on Computer Architecture Education, Las Vegas, NV, January 1998.
  • "Do Academics Require Access to DBMS Source Code in Order To Do Effective Research in the Area of Computer Architecture for Commercial Workloads?",
    First Workshop on Computer Architecture Evaluation Using Commercial Workloads, Las Vegas, NV, January 1998.
  • "Multiprocessor Applications for IRAM", First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
  • "Paths to the Petaflops Architecture", The 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers'96), Annapolis, Maryland, October 1996.
  • "Shared-Disk, Shared-Nothing, and Shared-Memory Architectures", First Intel Server Forum, Hillsboro OR, June 1996.
  • "What are the Minimal Elements of a Computer Engineering or Computer Science Curriculum?", 2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
  • "Hot Research Topics in Processor Architecture and in Shared Memory Multiprocessor Architecture", 1st Workshop on Computer Architecture, Paris, France, June 1995.

Talks at Workshops

  • "What the Parallelism Center Accomplished", at 2013 Illinois Symposium on Parallelism: Current State of the Field and the Future, Urbana, IL, September 2013.
  • "Parameter Variation at NT Voltage: The Power Efficiency versus Resilience Tradeoff", at DARPA PERFECT Program Meeting, Arlington, VA, February 2013.
  • "The Illinois Parallelism Center", at Microsoft Faculty Summit, Seattle, WA, July 2012.
  • "Toward Programmable Extreme Scale Computing", NSF/CISE Workshop on Cross-Layer Power Optimization and Management (CPOM), Los Angeles, CA, February 2012.
  • "Thrifty: An Exascale Architecture for Energy-Proportional Computing", at Exascale Research Meeting, DOE Office of Advanced Scientific Computing Research, San Diego, CA, March 2011.
  • "Accelerating Single-Thread Execution with Low Design Complexity: The BubbleWrap Approach", at Workshop on Advancing Computer Architecture Research (ACAR), What Now in ILP Research?, Seattle, WA, September 2010.
  • "Update on the Bulk Multicore Architecture", at Universal Parallel Computing Research Center (UPCRC) and Illinois Intel Parallelism Center (I2PC) Summits and Workshops: Santa Clara, CA (August 2008); Urbana, IL (February 2009); Hillsboro, OR (August 2009); Urbana, IL (March 2010); Seattle, WA (August 2010); Urbana, IL (April 2011); Santa Clara, CA (August 2011); Hillsboro, OR (December 2011); Seattle, WA (July 2012); Santa Clara, CA (August 2012); Urbana, IL (September 2013).
  • "The Architecture Needs to be Designed for Programmability", at Workshop on Advancing Computer Architecture Research (ACAR), Failure is not an Option: Popular Parallel Programming, San Diego, CA, February 2010.
  • "High-Speed, Transparent, Scalable Checkpointing", at Intel Workshop on New Memory Technologies, Hillboro, OR, January 2010.
  • "Simple Architectural Support to Check for Determinism", at Workshop on Determinism, Seattle, WA, December 2009.
  • "The Bulk Compiler", Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Multicore Architectures for Programmability, Hillsboro, OR, August 2009.
  • "Extreme Scale Architectures for Programmability", at DARPA-IPTO Workshop on Ubiquitous High Performance Computing, Stanford, CA, August 2009.
  • "High-Performance Parallel Computer Architectures", at Workshop on Careers in High Performance Systems Mentoring, Urbana, IL, July 2009.
  • "Multiprocessor Architectures for Programmability", at DARPA-IPTO Workshop on Exascale Ubiquitous High Performance Computing, University of Notre Dame, IN, April 2009.
  • "The Bulk Multicore Architecture for Programmability", at Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Multicore Computer Architecture for 2015, Urbana, IL, February 2009.
  • "The Bulk Multicore Architecture for Programmability", at Intel/Microsoft/Illinois/Berkeley UPCRC Workshop on Computer Architecture, Santa Clara, CA, August 2008.
  • "How Do We Use 50-Billion Transistors on a Chip?", at Workshop on The 50 Billion Transistor Challenge, IBM T.J. Watson Research Center, Yorktown Heights, NY, July 2008.
  • "An Updated Evaluation of ReCycle", at Workshop on Duplicating, Deconstructing, and Debunking, Beijing, China, June 2008.
  • "Speculative Multithreaded Architectures", at Workshop on Architectures and Compilers for Multithreading, Indian Institute of Technology, Kanpur, India, December 2007.
  • "Terascale-Level Multicore Processor Architectures: Promises and Roadblocks", at Workshop on Terachip Codesign, Defense Science Research Council (DSRC), Arlington, VA, October 2007.
  • "Colorama: Supporting the Data-Centric Synchronization Model", at Workshop on Directions in Multi-Core Processor Research, Microsoft Research, Redmont, WA, January 2007.
  • "Metrics for Processor Complexity", at Workshop on Complexity-Effective Design (WCED), in conjunction with ISCA, June 2005.
  • "Modern Rollback Techniques", at DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design, Menlo Park, CA, February 2005.
  • "New Architectural Technologies for Shared-Memory Systems", at DOE Salishan High Speed Computing Conference, Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "The FlexRAM Intelligent Memory System", at the Workshop on the Implementation of Multi-PIM Systems (WIMPS), Bodega Bay, CA, February 2002.
  • "Hardware for Speculative Parallelization in High-End Multiprocessor", at The Third PetaFlop Workshop (TPF-3), Annapolis, MD, February 1999.
  • "New Multithreading Architectures", at Internal IBM Workshop on Next Generation Processor Architectures, IBM Rochester, Rochester, MN, September 1998.
  • "Hardware for Speculative Parallelization in Large- and Small-Scale Multiprocessors", at Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
  • "Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors", at Seventh Workshop on Scalable Shared Memory Multiprocessors, Barcelona, June 1998.
  • "Computer Architecture Education at the University of Illinois", at 5th Annual Workshop on Computer Architecture Education, Barcelona, Spain, June 1998.
  • "COTS-Based Route to Petaflops Systems", at Petaflops Systems Operations Working Review (POWR), Bodega Bay, CA, June 1998.
  • "FlexRAM: Advanced Intelligent Memory", at Data Intensive Computing Systems, DARPA PI Meeting, Del Mar, CA, February 1998.
  • "How Processor-Memory Integration Affects the Design of DSMs", at First Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, June 1997.
  • "A COTS-Based Petaflops Design", at 1997 Petaflops Algorithms Workshop (PAL'97), Williamsburg, VA, April 1997.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at Workshop on the Petaflop Frontier, Annapolis MD, October 1996.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at First Intel Server Forum, Hillsboro OR, June 1996.
  • "The Illinois Aggressive Cache Only Memory Architecture Multiprocessor", at Petaflops Architecture Workshop (PAWS'96), Oxnard CA, April 1996.
  • "Computer Architecture Education at the University of Illinois: Current Status and Some Thoughts", at 2nd Annual Workshop on Computer Architecture Education, San Jose, California, February 1996.
  • "The Illinois Aggressive COMA Multiprocessor", at 1st Workshop on Computer Architecture, Paris, France, June 1995.
  • "Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors", at Third Workshop on Scalable Shared-Memory Multiprocessors, San Diego, CA, May 1993.
  • "The Cache Behavior of Shared Data in Cache-Coherent Multiprocessors", at First Workshop on Scalable Shared-Memory Multiprocessors, Seattle, WA, May 1989.

Participation in Other Workshops and Meetings

  • "ARM Research Summit", Cambridge, UK, September 2016.
  • "Nanotechnology-Inspired Information Processing Systems Workshop", Washington, DC, August 2016.
  • "Computing Beyond 2025 Summit", Argonne National Laboratory, August 2016.
  • "Arch2030: A Vision of Computer Architecture Research over the Next 15 Years Workshop", Seoul, Korea, June 2016.
  • "CCC Symposium on Computing Research Addressing National Priorities and Societal Needs", Washington, DC, May 2016.
  • "Computing Innovation Fellows (CIFellows) Workshop", San Francisco, CA, May 2014.
  • "A Day at Technion", Technion, Haifa, Israel, June 2013.
  • "30 Years of Parallel Computing at Argonne", Argonne National Laboratory, IL, May 2013.
  • "DARPA PERFECT Program Meeting": Arlington, VA, February 2013; Arlington, VA, July 2013; Berkeley CA, January 2014.
  • "DOE Exascale Research Conference": San Diego, CA, March 2011; Annapolis, MD, October 2011; Portland, OR, April 2012; Portland, OR, September 2012; Berkeley, CA, March 2013.
  • "ACS Productivity Workshop", DOD, Ford Meade, MD, July 2011.
  • "Universal Parallel Computing Research Center (UPCRC) and Illinois Intel Parallelism Center (I2PC) Summits and Workshops": Santa Clara, CA (August 2008); Urbana, IL (February 2009); Hillsboro, OR (August 2009); Urbana, IL (March 2010); Seattle, WA (August 2010); Urbana, IL (April 2011); Santa Clara, CA (August 2011); Hillsboro, OR (December 2011); Seattle, WA (July 2012); Santa Clara, CA (August 2012); Urbana, IL (September 2013).
  • "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2010.
  • "Google Day", San Jose, CA, July 2008.
  • "Research@Intel Day", Mountain View, CA, June 2008.
  • "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2008.
  • "DOE/DOD Workshop on Emerging High Performance Architectures & Applications", Washington, DC, November 2007.
  • "Workshop on Computer Academic/Industry Architecture Consortium (CAIAC)", Austin, TX, September 2007.
  • "Microsoft Faculty Summit", Redmond, WA, July 2007.
  • "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2006.
  • "Computing Research Associtation (CRA) Conference on Grand Research Challenges: Revitalizing Computer Architecture Research", Monterey Bay, CA, December 2005.
  • "Intel Multi-Core University Research Conference", Portland, OR, December 2005.
  • "NSF-CISE Area Review. Area of Computer Architecture and Organization", NSF, May 2005.
  • "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2005.
  • "DARPA-Sponsored Information Science and Technology (ISAT) Study on Law of Large Numbers System Design", Menlo Park, CA, February 2005.
  • "Meeting of Lead PIs of Medium and Large Projects in the Information Technology Research (ITR) NSF Program", Washington, June 2004.
  • "DOE Salishan High Speed Computing Conference", Salishan Lodge, Gleneden Beach, OR, April 2004.
  • "Workshop on Software for Processor-In-Memory Based Parallel Systems", San Jose, CA, March 2004.
  • "Science Case for Large-scale Simulation," DOE Workshop, Washington, June 2003.
  • "Review Panel of the Programa Ramon y Cajal for Returning Scientists", Government of Spain, Madrid, June 2003.
  • "Performance Analysis and Distributed Computing (PADC 2002)", Dagstuhl Seminar, Dagstuhl, Germany, August 2002.
  • "Performance Engineering Technology & Research Sponsored Under the NSF Next Generation Software Program", Austin, TX, February 2002.
  • "Workshop on the Implementation of Multi-PIM Systems (WIMPS)", Bodega Bay, CA, February 2002.
  • "Review Panel of the Programa Ramon y Cajal for Returning Scientists", Government of Spain, Madrid, September 2001.
  • "All Hands NCSA Meeting", Urbana, IL, May 2001.
  • "NSF-CCR Workshop on Research Directions for Next-Generation Systems Design and Integration", Seattle, WA, June 1999.
  • "NCSA Alliance Technical Working Meeting", Oak Brooks, IL, May 1999.
  • "The Third PetaFlop Workshop (TPF-3)", Annapolis, MD, February 1999.
  • "IBM Workshop on Next Generation Processor Architectures", IBM Rochester, Rochester, MN, September 1998.
  • "Petaflops Systems Operations Working Review (POWR)", Bodega Bay, CA, June 1998.
  • "Research Workshop between the University of Illinois at Urbana-Champaign and the Centre National de la Recherche Scientifique (CNRS) of France", Urbana, IL, April 1998.
  • "National Computational Science Alliance (NCSA) Alliance'98 Conference", Urbana, IL, April 1998.
  • "Petaflops Algorithms Workshop (PAL'97)", Williamsburg, VA, April 1997.
  • "Workshop on the Petaflop Frontier", Annapolis MD, October 1996.
  • "DARPA ITO General PI Meeting", Dallas, TX, October 1996
  • "DARPA Workshop on Performance Evaluation", Washington DC, September 1996.
  • "NSF Experimental Research Workshop", Washington DC, June 1996.
  • "Petasoft: Software for Petaflop Machines", Bodega Bay CA, June 1996.
  • "First Intel Server Forum", Hillsboro OR, June 1996.
  • "PetaFlops Architecture Workshop PAWS'96", Oxnard CA, April 1996
  • "1st Workshop on Computer Architecture", Paris, France, June 1995.

Graduate Students

  • Granted 36 Ph.D. Degrees:
    • Wooil Kim, 2015. First Job: Member of Technical Staff, Samsung Electronics, Seoul, Korea. Thesis: Architecting, Programming, and Evaluating an On-Chip Incoherent Multiprocessor Memory Hierarchy.
    • Nima Honarmand, 2014. First Job: Assistant Professor, Department of Computer Science, Stony Brook University, Stony Brook, NY. Thesis: "Record and Deterministic Replay of Parallel Programs on Multiprocessors".
    • Aditya Agrawal, 2014. First Job: Member of Research Staff, NVidia, Santa Clara, CA. Thesis: "Refresh Reduction in Dynamic Memories".
    • Yuelu Duan, 2014. First Job: Member of Technical Staff, VMware, San Diego, CA. Thesis: "Techniques for Low Overhead Fences and Sequential Consistency Violation Recording".
    • Xuehai Qian, 2013. Current Job: Assistant Professor, Department of Electrical Engineering, University of Southern California, Los Angeles, CA. Thesis: "Scalable and Flexible Bulk Architecture".
    • Shanxiang Qi, 2013. First Job: Member of Technical Staff, Google, Mountain View, CA. Thesis: "Techniques to Detect and Avert Advanced Software Concurrency Bugs".
    • Ulya Karpuzcu, 2012. First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN. Thesis: "Novel Many-Core Architectures for Energy-Efficiency".
    • Abdullah Muzahid, 2012. First Job: Assistant Professor, Department of Computer Science, University of Texas at San Antonio, San Antonio, TX. Thesis: "Effective Architectural Support For Detecting Concurrency Bugs".
    • Daniel Wonsun Ahn, 2012. Current Job: Assistant Professor, Department of Computer Science, University of Pittsburgh, Pittsburgh, PA. Thesis: "Software and Architecture Support for the BULK Multicore".
    • Pablo Montesinos, 2009. First Job: Member of Research Staff, Samsung Laboratories, San Jose, CA. Thesis: "Practical Time Travel of Multiprocessor Systems".
    • Brian Greskamp, 2009. First Job: Member of Research Staff, D. E. Shaw Research, New York, NY. Thesis: "Improving Per-Thread Performance on CMPs through Timing Speculation."
    • Radu Teodorescu, 2008. First Job: Assistant Professor, Department of Computer Science and Engineering, Ohio State University, Columbus, OH. Thesis: "Multilayer Techniques to Address Parameter Variation".
    • Abhishek Tiwari, 2008. First Job: Member of Technical Staff, Goldman Sachs, New York, NY. Thesis: "Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors".
    • Luis Ceze, 2007. First Job: Assistant Professor, Department of Computer Science and Engineering, University of Washington, Seattle, WA. Thesis: "Bulk Operation and Data Coloring for Multiprocessor Programmability".
    • James Tuck, 2007. First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC. Thesis: "Efficient Support for Speculative Tasking".
    • Karin Strauss, 2007. First Job: Member of Research Staff, AMD Laboratories, Seattle, WA. Thesis: "Cache Coherence in Embedded-Ring Multiprocessors".
    • Smruti R. Sarangi, 2007. Current Job: Assistant Professor, Department of Computer Science and Engineering, Indian Institute of Technology, New Delhi, India. Thesis: "Techniques to Mitigate the Effects of Congenital Faults in Processors".
    • Jun Nakano, 2006. First Job: Member of Research Staff, IBM Research, Tokyo, Japan. Thesis: "Techniques to Address Unreliability and Variability of Computing Systems".
    • Jose Renau, 2004. First Job: Assistant Professor, Department of Computer Engineering, University of California, Santa Cruz. Thesis: "Chip Multiprocessors with Speculative Multithreading: Design for Performance and Energy Efficiency".
    • Milos Prvulovic, 2003. First Job: Assistant Professor, College of Computing, Georgia Institute of Technology, Atlanta, GA. Thesis: "Architectural Support for Reliable Parallel Computing".
    • Jose Martinez, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY. Thesis: "Speculative Shared-Memory Architectures".
    • Yan Solihin, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC. Thesis: "Improving Memory Performance Using Intelligent Memory."
    • Michael Huang, 2002. First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY. Thesis: "Managing Processor Adaptation for Energy Reduction and Temperature Control".
    • Anthony Nguyen, 2002. Current Job: Member of Research Staff, Intel Corporation, Santa Clara, CA. Thesis: "High-Throughput Coherence Controllers".
    • Marcelo Cintra, 2001. First Job: Lecturer, School of Informatics, University of Edinburgh, UK. Thesis: "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors".
    • Seung-Moon Yoo, 2001. First Job: Member of Research Staff, IBM Research, Austin, TX. Thesis: "Design of Energy-Efficient SOCs with Deep Sub-Micron Circuit Techniques".
    • Qiang Cao, 2000. First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA. Thesis: "Performance Characterization and Buffer Memory Optimization of Databases".
    • Sujoy Basu, 2000. First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA. Thesis: "Design of Efficient Simple COMA Architectures".
    • Yi Kang, 1999. First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA. Thesis: "An Intelligent Memory for Data Intensive Applications".
    • Ye Zhang, 1999. First Job: Member of Technical Staff, Oracle Corporation, Redwood Shores, CA. Thesis: "Speculative Parallelization in DSM Multiprocessors".
    • Pedro Trancoso, 1998. Current Job: Lecturer, Department of Computer Science, University of Cyprus, Cyprus. Thesis: "Optimizing Memory-Resident DSS Workloads for Caches".
    • Venkata Krishnan, 1998. First Job: Microprocessor Design Group, DEC Shrewsbury, MA. Thesis: "Speculative Multithreading Architectures".
    • Liuxi Yang, 1997. First Job: Microprocessor Design Group, Sun Microsystems, Menlo Park, CA. Thesis: "Using Advanced Memory Technologies to Build DSM Multiprocessors."
    • David Koufaty, 1997. First Job: Member of Technical Staff, Intel Corp, Hillsboro, OR. Thesis: "Compiler Support to Hide Coherence Misses in Shared-Memory Multiprocessors".
    • Zheng Zhang, 1996. First Job: Member of Research Staff, Hewlett-Packard Laboratories, Palo Alto, CA. Thesis: "Design Alternatives to Reduce Remote Conflict Misses in Shared-Memory Multiprocessors".
    • Chun Xia, 1996. First Job: Member of Technical Staff, Sun Microsystems, Menlo Park, CA. Thesis: "Exploiting Multiprocessor Memory Hierarchies for Operating Systems."

  • Granted M.S. Degrees:
    • Russell Daigle, Xiangfeng Chen, David Oesterreich, Alain Raynaud, Kittipong Mungnirun, Pedro Trancoso, Arun Sharma, Jovan Mitrevski, Jose Martinez, Zhenzhou Ge, Michael Huang, Yan Solihin, Jose Renau, Milos Prvulovic, Vinh Lam, James Tuck, Kuan Chen, Smruti Sarangi, Radu Teodorescu, Paul Sack, Brian Greskamp, Pablo Montesinos, Abdullah Muzahid, Ulya Karpuzcu, Shanxiang Qi, Rishi Agarwal, Marios Nicolaides, Ben Ahrens, Raghavendra Pothukuchi, Mengjia Yan, Tanmay Gangwani, Dimitrios Skarlatos, Ali Bohloolizamani, Yasser Shalabi.

Postdoctoral Researchers and Visitors

  • Postdoctoral Researchers
    • Sanyam Mehta, Oct 2014 - pres.
      University of Minnesota, USA
    • Wonsun Ahn, Apr 2012 - Aug 2014
      University of Illinois, USA
    • Amin Ansari, Sep 2011 - Aug 2013
      University of Michigan, USA
    • Wei Liu, Aug 2001 - Aug 2006
      Tsinghua University, China
    • Basilio Fraguela, Aug 2001 - Aug 2002
      Universidade A Coruna, Spain

  • Visiting Scientists
    • Oscar Plata, Sep 2015 - Nov 2015
      Universidad de Malaga, Spain.
    • Sonia Gonzalez, Sep 2015 - Nov 2015
      Universidad de Malaga, Spain.
    • Sergi Abadal, May 2015 - Nov 2015
      Universitat Politecnica de Catalunya, Spain.
    • Benjamin Sanhelices, Aug 2010 - Dec 2010
      Universidad de Valladolid, Spain.
    • Lois Orosa, Sep 2009 - Dec 2009
      Universidad de Santiago, Spain.
    • Norimasa Otsuki, Aug 2009 - Aug 2010
      Renesas Technology, Japan.
    • Dario Suarez, May 2008 - Jul 2008
      Universidad de Zaragoza, Spain
    • Daniel Chaver, Jul 2002 - Aug 2002
      Universidad Complutense de Madrid, Spain
    • Keiji Kimura, Aug 2001 - Oct 2001
      Waseda University, Japan
    • Pedro Trancoso, Jul 2000 - Aug 2000
      International College, Limassol, Cyprus
    • Jaejin Lee, Aug 1999 - Dec 1999
      Michigan State University, MI
    • Paul Feautrier, Feb 1999 - May 1999
      Universite de Versailles, Versailles, France
    • Diego Llanos, May 1999 - Jul 1999
      Universidad de Valladolid, Valladolid, Spain
    • Josep Lluis Larriba-Pey, Apr 1996 - Sep 1996, Jul 1997 - Sep 1997
      Universitat Politecnica de Catalunya, Barcelona, Spain

Teaching Activity

  • Extensive teaching and advising experience at the undergraduate and graduate levels. Taught undergraduate- and graduate-level courses on computer architecture, computer organization, and logic design at UIUC
  • Invited to talk about "Computer Architecture Education at the University of Illinois" at the 2nd, 4th, and 5th Annual Workshop on Computer Architecture Education, February 1996, January 1998, and June 1998
  • Appeared several times in the local student newspaper Daily Illini under "Incomplete List of Teachers Ranked Excellent By Their Students"
  • Some of the courses taught were being broadcasted to large off-campus audiences, both in the U.S. and in India
  • Organized the weekly Illinois-Intel Parallelism Center (I2PC) Distinguished Speaker Seminar (August 2011 - August 2013) and invited many Intel personnel to speak.
  • Created a graduate-level weekly research seminar: "Research Topics in Advanced Computer Architecture"
  • Developed semester-long special-topics courses: "Shared-Memory Multiprocessors: Architecture and Programming" (Spring 93) and "Research Issues in New Processor and Memory Architectures" (Spring 01)

Other Major Service Outside UIUC

  • Member, Selection Committee for the IEEE Harry Goode Award, March 2016.
  • Participant in many NSF, DOE, and DARPA workshops, PI meetings, and program-conception meetings, including DARPA's "Data Intensive Systems", "Bio-Computation", "Polymorphous Computer Architectures", "High Productivity Computer Architectures", "Ubiquitous High Performance Computing", and "Power Efficiency Revolution for Embedded Computing Technology".
  • Presented the outcome of Computing Community Consortium (CCC) workshops to CCC, DOE, NSF, AFOSR, and NITRD.
  • CCC-appointed liaison to guide the visioning workshops on "Charting the Future of Electronic Design Automation", March 2013, June 2013, and February 2014.
  • Member of the Steering Committee, IEEE Computer Society Multicore, April 2013 - pres.
  • Member of the IEEE Fellows Selection Committee, 2012, 2013, 2016.
  • Member, Computing Innovation Fellows Selection Committee, CCC and CRA, 2010.
  • Member, Search Committee for the Editor-in-Chief of the Computer Architecture Letters (CAL) journal, 2005.
  • Participant, Site Visit for NSF Expeditions in Computing, December 2015.
  • Participant in many NSF Proposal Evaluation Panels: March 1996, November 1998, March 2000, July 2001, February 2002, February 2003, May 2004, August 2004, October 2007, April 2008, December 2008, April 2009, March 2010, December 2010, March 2011, March 2012, May 2013, June 2014.
  • Member of the Advisory Board, Department of Electrical and Computer Engineering, University of Rochester, 2003-pres.
  • Member of Enabling Technologies Team A, NSF's National Computational Science Alliance (NCSA) Partnership for an Advanced Computational Infrastructure (PACI), 1997 - 2004.
  • I-ACOMA research project was selected as one of the "Eight Point-Design Studies" that DARPA, NSF, NSA and NASA supported in 1996 in a nationwide effort to accelerate the arrival of a petaflop-level machine.
  • Regular referee for the major conferences and journals in computer architecture and parallel processing, and reviewer of books on computer architecture.

Major Service Inside UIUC

  • Member of the Advisory Board, IBM-Illinois Center for Cognitive Computing Systems Research, April 2016.
  • Member, Search Committee for Associate Dean for Graduate, Professional, and Online Education, College of Engineering, March 2016.
  • Member of College of Engineering Executive Committee (2002-2008) and Grievance Committee (2002-3, 2006-7).
  • Served in many special committees at the College of Engineering.
  • Served in many committees at the Department of Computer Science: Promotions and Tenure; Faculty Recruiting; Chairs and Professorships; Faculty Awards; Advisory; Distinguished Lecture and Departmental Seminar; Fellowships, Assistantships and Graduate Admissions; Computing and Technology Advisory; Task Force on Graduate Student Weekend; Courses and Curriculum; Undergraduate Study; Graduate Advising; Undergraduate Advising; TEI; Graduate Research Orientation; Standing Subcommittee on Engineering/Chemistry Liaison; Computer Affiliates Program; Search Committee for the Director of Budget and Resource Planning; CSL Computing and Networking; and CSRD Industrial Affiliates Program.
  • Member, Computer Science Department Head Review Committee, 2015.
  • Chair, Architecture, Compilers, and Parallel Computing Area, Department of Computer Science, 2004, 2005, 2016, 2017.
  • Member, Parallel Computing Institute (PCI) Growth Committee, 2013-pres.
  • Host to many speakers and visitors invited to the Department of Computer Science.
  • Participated and organized faculty retreats for the Computer Science Department, Computer Engineering, and College of Engineering.
  • Participated in several Illinois Computer Science Alumni reunions across the nation.

Other Activities

  • Consultant for several companies.
  • Consultant for patent assessment. Member of the Round Table Group (RTG) Network of Patent Consultants.