March 2016: Torrellas elected to
the Computing Research Association (CRA)
Board of Directors.
January 2016: Torrellas named Saburo Muroga Professor of Computer Science at the
University of Illinois at Urbana-Champaign.
The i-acoma Architecture Group, led by Professor Josep Torrellas, focuses on new processor, memory, and system technologies and organizations to build novel multiprocessor computer architectures. The two main projects are:
- A novel multicore architecture for programmability:
The Bulk Multicore Architecture (Communications of the ACM, December 2009). [Presentation slides].
EE Times article that discusses the Bulk Multicore.
Dr. Dobb's Journal discussion of the Bulk Multicore.
Making Parallel Programming Easy: Research Contributions from Illinois, a book summarizing the accomplishments of the Illinois-Intel Parallelism Center (I2PC).
This project is funded by Intel under the Illinois Intel Parallelism Center (I2PC).
- An extreme-scale multiprocessor architecture designed from the
ground up for energy and power efficiency:
Thrifty: An Extreme-Scale Multiprocessor Architecture (IEEE Computer, November 2009). [Presentation slides].
Extreme-Scale Computer Architecture: Energy Efficiency from the Ground Up (DATE, March 2014).
This work is part of an Intel-lead DARPA project that aims to design an Extreme-Scale computer.
Intel blog on the DARPA project.
This project is funded by DARPA under UHPC and DOE.
Recent Designed Architectures:
- "QuickRec: A Hardware Prototype for Recording and Deterministically Replaying Multithreaded Programs in the Intel Architecture". This prototype has been developed in collaboration with Intel, and is described in the QuickRec ISCA-2013 paper.
- "Runnemede: An Chip Multiprocessor for Extreme-Scale Computing". This manycore chip has been designed in collaboration with Intel, and is described in the Runnemede HPCA-2013 paper.
The emphasis research areas in the group are:
- Multiprocessor organization and system design
- Speculative multithreading
- Hardware reliability and variability
- Support for software reliability
- Low-power design
- Old Projects
We have released these software tools:
- VARIUS: A model of within-die process variation and resulting timing errors in processors for microarchitects.
- SESC: A cycle accurate architectural simulator that models a very wide set of architectures: superscalars, multiprocessors, processors in memory, and thread-level speculation.
Our research is funded by NSF, DARPA, and DOE.